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author | Joe McGill <jmcgill@us.ibm.com> | 2018-05-24 17:54:52 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-09-20 22:22:13 -0500 |
commit | ed95ad23449b85791d32c9b171c41d254e989f92 (patch) | |
tree | 7941ecaa26e66979f0147b2c17512efec6976165 /src | |
parent | ff74130fcca2fb5f83739ca03f7b310ea8356c36 (diff) | |
download | talos-sbe-ed95ad23449b85791d32c9b171c41d254e989f92.tar.gz talos-sbe-ed95ad23449b85791d32c9b171c41d254e989f92.zip |
FBC ABUS TDM inject and recovery HWPs
p9_fbc_ioo_tdm_inject
New HWP to permit concurrent maintenance of an SMP OBUS link
(full-width to half-width operation)
Specified half-link of provided endpoint target will have:
- FIRs masked
- DL layer quiesced
- PHY powered down
FW should set i_opts members as follows:
- i_opts.run_all=true -- HWP executes all steps
- i_opts.step=P9_FBC_IOO_TDM_INJECT_END -- don't care
p9_fbc_ioo_tdm_recovery
New HWP to permit concurrent maintenance of an SMP OBUS link
(half-width to full-width operation)
HWP detects half-link to recover from provided enpoint target. Specified
half-link will have:
- FIRs masked and reset
- DL layer reset
- PHY layer reset, dccal run, and re-initialized
- DL FIRs cleared
- DL started and retrained
- FIRs unmasked
FW should set i_opts members as follows:
- i_opts.run_all=true -- HWP executes all steps
- i_opts.even_not_odd=true -- don't care
- i_opts.step=P9_FBC_IOO_TDM_RECOVERY_END -- don't care
p9_security_white_black_list
Add greylist entries for OBUS PHY, DL layer FIR and FIR mask registers
p9_io_regs
Add register constants needed for link recovery
p9_io_obus_reset
Clear RX and TX ioreset
Add inits specified in SCOM initfile used at initial IPL
p9_obus_fir_utils
Add constants to reflect grey list entries for OBUS FIRs
p9_io_obus_scominit
p9_chiplet_scominit
Reference p9_obus_fir_utils for OBUS FIR programming values
Change-Id: Iad3884f6057c2ca21f436bc6efc0423fb5f70226
CQ: SW446137
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59370
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63633
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/import/chips/p9/security/p9_security_white_black_list.csv | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/import/chips/p9/security/p9_security_white_black_list.csv b/src/import/chips/p9/security/p9_security_white_black_list.csv index afb0e0ad..9ae1246a 100644 --- a/src/import/chips/p9/security/p9_security_white_black_list.csv +++ b/src/import/chips/p9/security/p9_security_white_black_list.csv @@ -202,7 +202,6 @@ Version,Chiplet,Base Address,Chiplet Id - range,Bit Mask,User,Register Name,Desc ,XBUS,0000000006011C0B,0x06,,HB,PowerBus ELL Control register,,write_whitelist, ,XBUS,000000000601200B,0x06,,HB,PowerBus ELL Control register,,write_whitelist, ,OBUS,000000000901080B,0x09-0x0C,FF0FFFFFFF0FFFFF,HWSV,PowerBus OLL Control register,,write_greylist, -,OBUS,0000000009010800,0x09-0x0C,00000000000C0000,HWSV,PowerBus OLL FIR register,,write_greylist, ,OBUS,000000000901080C,0x09-0x0C,,HWSV,PowerBus OLL PHY Training Config register,,write_whitelist, ,OBUS,000000000901080F,0x09-0x0C,,HWSV,PowerBus OLL Optical Config register,,write_whitelist, ,OBUS,0000000009010810,0x09-0x0C,,HWSV,PowerBus OLL TX0 Lane Control register,,write_whitelist, @@ -212,6 +211,10 @@ Version,Chiplet,Base Address,Chiplet Id - range,Bit Mask,User,Register Name,Desc ,OBUS,8000080009010C3F,0x09-0x0C,,HWSV,rx(tx)_lane_ana_pdwn rx_lane_dig_pdwn and rx_lane_disabled,,write_whitelist, ,Core,0000000020010A9C,0x20-0x37,,HB,Direct injects into logic - no latches!!,,write_whitelist, ,Core,0000000020010A9D,0x20-0x37,,HB,RAS Mode Register,,write_whitelist, +,OBUS,0000000009010C00,0x09-0x0C,FFFFFFFFFFFFC000,HWSV,OBUS PHY FIR register,,write_greylist, +,OBUS,0000000009010C03,0x09-0x0C,FFFFFFFFFFFFC000,HWSV,OBUS PHY FIR Mask register,,write_greylist, +,OBUS,0000000009010800,0x09-0x0C,FFFFFFFFFFFFDFFC,HWSV,PB PowerBus Optical DL FIR register,,write_greylist, +,OBUS,0000000009010803,0x09-0x0C,FFFFFFFFFFFFDFFC,HWSV,PB PowerBus Optical DL FIR Mask register,,write_greylist, ,XBUS,8000000006010C3F,0x06,,HB,,,write_whitelist, ,XBUS,8000000106010C3F,0x06,,HB,,,write_whitelist, ,XBUS,8000000206010C3F,0x06,,HB,,,write_whitelist, |