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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-10-06 14:38:51 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-10-09 11:21:31 -0400 |
| commit | ec9a99e9c39564fc9a69589d2bed3f339b0e86b1 (patch) | |
| tree | d6e2af52d54c907578bcce8d0f3e36b9ee3323d8 /src | |
| parent | b00f996cce04424af4dc38a112edcd6900e5de92 (diff) | |
| download | talos-sbe-ec9a99e9c39564fc9a69589d2bed3f339b0e86b1.tar.gz talos-sbe-ec9a99e9c39564fc9a69589d2bed3f339b0e86b1.zip | |
p9_sbe_chiplet_reset: Set VITL_AL flag for MC chiplets
There is a phase sync signal between the Nest and MC chiplets that is
only needed for combined synchronous LBIST of the inter-chiplet interface,
but can disrupt scanning in async MC operation. So it should be masked in
normal operation by setting the VITL_AL flag in NET_CTRL0.
Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251
CQ: HW422475
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: LENNARD G. STREAT <lstreat@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48057
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index e04d078e..938be1bd 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -363,6 +363,11 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ)); + + //Setting VITL_AL config bit to disable listening to cross-chiplet DDR sync signal + FAPI_DBG("Set VITL_AL for MC chiplet"); + FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR, + p9SbeChipletReset::NET_CNTL0_SET_VITL_AL)); } } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 1c4ffd0a..74b105f0 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -63,6 +63,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + NET_CNTL0_SET_VITL_AL = 0x0020000000000000ull, HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, HANG_PULSE_0X06 = 0x06, |
