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| author | Thi Tran <thi@us.ibm.com> | 2017-10-20 14:28:00 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-10-26 00:57:15 -0400 |
| commit | e15c80ad9743e5d5d9d6da585f0c598d00832930 (patch) | |
| tree | 68a045a9da50a33c9d2cc74a14d18b8aa813f5ee /src | |
| parent | 204fab916ae42cce6ec3942077b60c955e7e68ba (diff) | |
| download | talos-sbe-e15c80ad9743e5d5d9d6da585f0c598d00832930.tar.gz talos-sbe-e15c80ad9743e5d5d9d6da585f0c598d00832930.zip | |
Need to clear OCB3 errors before a PBA operation
Change-Id: Iaa7246b82bc490222162ef74011db78bc8631e23
CQ:SW405593
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48647
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48649
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C index 6e322113..ce44b090 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C @@ -199,11 +199,14 @@ extern "C" //Write the OCB3 Status Control Register //Configure linear stream mode (auto-increment +8 with each data register read/write) - //set bit 4 and unset bit 5 of OCB3 Status Control Register - ocb_status_ctl_data.flush<0>().setBit<5>(); + // Set bits 0:1 to clear PULL_READ_UNDERFLOW and PUSH_WRITE_OVERFLOW + // Set bit 5 to clear stream type (enables linear mode) + // Set bits 6:15 to clear other errors + ocb_status_ctl_data.flush<0>().setBit<0, 2>().setBit<5, 11>(); FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_CLEAR, ocb_status_ctl_data), "Error writing to the OCB3 Status Control Register with and mask"); + // Set bit 4 to enable stream mode ocb_status_ctl_data.flush<0>().setBit<4>(); FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_OR, ocb_status_ctl_data), |
