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| author | Srikantha Meesala <srikantha@in.ibm.com> | 2017-12-05 02:35:31 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-12-07 06:29:12 -0500 |
| commit | d9055c39cfed1665008b9a2597f643d3e462b4bd (patch) | |
| tree | b59be387f87b2a2ff2e92687abe4300898c0fd4a /src | |
| parent | 8e0caa8e381d9910dd4845612fe87ebce6602e5e (diff) | |
| download | talos-sbe-d9055c39cfed1665008b9a2597f643d3e462b4bd.tar.gz talos-sbe-d9055c39cfed1665008b9a2597f643d3e462b4bd.zip | |
Updated PSI and TOD regs into whitelist
Change-Id: I5b8afde659b1c9f7c4f527791efaafb88e03380b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50482
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50487
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/security/p9_security_white_black_list.csv | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/import/chips/p9/security/p9_security_white_black_list.csv b/src/import/chips/p9/security/p9_security_white_black_list.csv index 59d15022..24524a87 100644 --- a/src/import/chips/p9/security/p9_security_white_black_list.csv +++ b/src/import/chips/p9/security/p9_security_white_black_list.csv @@ -18,11 +18,14 @@ Version,Chiplet,Base Address,Chiplet Id - range,User,Register Name,Description/U ,TP,0x00040006,0x00,HWSV,TOD internal path control register,p9_tod_setup.C,write_whitelist, ,Nest 3,0x05013419,0x05,HWSV,PB Electrical Round-Trip Delay Control Register,p9_tod_setup.C,write_whitelist, ,TP,0x00040010,0x00,HWSV,TOD chip control register,p9_tod_setup.C,write_whitelist, +,TP,0x00040022,0x00,HWSV,TOD start fsm register,p9_tod_init.C,write_whitelist, ,Nest 3,0x05012913,0x05,HWSV,PSI Host Bridge Control/Status Register(CLEAR),hwcoProcPsiInit.C,write_whitelist, +,Nest 3,0x0501290E,0x05,HWSV,PSI Host Bridge Control/Status Register,hwcoProcPsiInit.C,write_whitelist, ,Nest 2,0x04011830,0x04,HWSV,PSI Tx Cntl Reg,hwcoProcPsiInit.C,write_whitelist, ,Nest 2,0x04011820,0x04,HWSV,PSI Rx Cntl Reg,hwcoProcPsiInit.C,write_whitelist, ,Nest 2,0x04011831,0x04,HWSV,PSI Tx Mode Reg,hwcoProcPsiInit.C,write_whitelist, ,Nest 2,0x04000019,0x04,HWSV,Chiplet Config Register 1,hwcoProcPsiInit.C,write_whitelist, +,Nest 2,0x04000029,0x04,HWSV,Chiplet Config Register Clear,hwcoProcPsiInit.C,write_whitelist, ,Nest 3,0x05012912,0x05,HWSV,PSI Host Bridge Control/Status Register(OR),hwcoProcPsiInit.C,write_whitelist, ,Nest 3,0x05012800,0x05,HWSV,PSI TX and Common Control Status Register,hwcoProcPsiInit.C,write_whitelist, ,Nest 3,0x05012808,0x05,HWSV,PSI RX Control Status Register,hwcoProcPsiInit.C,write_whitelist, @@ -31,6 +34,10 @@ Version,Chiplet,Base Address,Chiplet Id - range,User,Register Name,Description/U ,Nest 3,0x05012911,0x05,HWSV,PSI Host Bridge Debug Service Register,hwcoProcPsiInit.C,write_whitelist, ,Nest 3,0x0501280A,0x05,HWSV,PSI Rx Error Register,hwcoProcPsiInit.C,write_whitelist, ,Nest 3,0x05012802,0x05,HWSV,PSI Tx Error Register,hwcoProcPsiInit.C,write_whitelist, +,Nest 3,0x05012810,0x05,HWSV,PSI Tx Inta Register,hwcoProcPsiInit.C,write_whitelist, +,Nest 3,0x05012818,0x05,HWSV,PSI Rx Inta Register,hwcoProcPsiInit.C,write_whitelist, +,Nest 3,0x05012813,0x05,HWSV,PSI Tx Misc Register,hwcoProcPsiInit.C,write_whitelist, +,Nest 3,0x0501281B,0x05,HWSV,PSI Rx Misc Register,hwcoProcPsiInit.C,write_whitelist, ,MC,0x070123DB,0x07-0x08,HWSV,MCBIST Control Register,lib/dimm/ccs.H,write_whitelist, ,MC,0x070123A7,0x07-0x08,HWSV,MCP Configured Command Sequence Mode Register,lib/dimm/ccs.H,write_whitelist, ,MC,0x8000C0110701103F,0x07-0x08,HWSV,,lib/dimm/rank.H,write_whitelist, |
