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author | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-01-23 21:31:10 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-01-24 06:08:06 -0500 |
commit | d737f8e95da3aabb73cc60085cdbad9c05600f48 (patch) | |
tree | 6d2b7cfc55eca3815fe51284f7cd91d1ada11f58 /src | |
parent | 9b03db45c424d6edc5698fa74830dc1d432fdfe8 (diff) | |
download | talos-sbe-d737f8e95da3aabb73cc60085cdbad9c05600f48.tar.gz talos-sbe-d737f8e95da3aabb73cc60085cdbad9c05600f48.zip |
Allow read on complete OCC SRAM buffer
Change-Id: Ife2f4a321753f6367e2cfa0ee9fd3804a4d8d52a
CQ: FW672705
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52499
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/sbefw/core/sbeSecureMemRegionManager.H | 11 | ||||
-rw-r--r-- | src/sbefw/core/sbecmdsram.C | 6 | ||||
-rw-r--r-- | src/sbefw/core/sbeglobals.H | 2 | ||||
-rw-r--r-- | src/test/testcases/testSram.py | 23 |
4 files changed, 20 insertions, 22 deletions
diff --git a/src/sbefw/core/sbeSecureMemRegionManager.H b/src/sbefw/core/sbeSecureMemRegionManager.H index 1d5fc4bd..c049fc2c 100644 --- a/src/sbefw/core/sbeSecureMemRegionManager.H +++ b/src/sbefw/core/sbeSecureMemRegionManager.H @@ -5,7 +5,8 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -41,12 +42,9 @@ typedef struct uint32_t mode; } secureMemRegion_t; -// OCC SRAM Command buffer +// OCC SRAM Command buffer ( R/W access ) constexpr uint64_t OCC_CMD_ADDR = 0xFFFBE000ull; constexpr uint32_t OCC_CMD_SIZE = 0xFFFBEFFF - 0xFFFBE000; -// OCC SRAM Response buffer -constexpr uint64_t OCC_RESP_ADDR = 0xFFFBF000ull; -constexpr uint32_t OCC_RESP_SIZE = 0xFFFBFFFF- 0xFFFBF000; class SBESecureMemRegionManager { @@ -130,9 +128,6 @@ class SBEOccSramSecMemRegionManager : public SBESecureMemRegionManager OCC_CMD_SIZE, static_cast<uint8_t>( memRegionMode::WRITE) | static_cast<uint8_t>(memRegionMode::READ)); - add(OCC_RESP_ADDR, - OCC_RESP_SIZE, - static_cast<uint8_t>(memRegionMode::READ)); } // Disable copy constructors diff --git a/src/sbefw/core/sbecmdsram.C b/src/sbefw/core/sbecmdsram.C index ce05f7f6..0a57dca8 100644 --- a/src/sbefw/core/sbecmdsram.C +++ b/src/sbefw/core/sbecmdsram.C @@ -5,7 +5,8 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -135,7 +136,8 @@ uint32_t sbeOccSramAccess_Wrap(const bool i_isGetFlag) } CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc); // Check if the access to the address is allowed - if(l_validAddrForFirstAccess) + // For read access no checking is required + if( (l_validAddrForFirstAccess) && !( i_isGetFlag )) { l_respHdr.secondaryStatus = occSramSecRegionManager.isAccessAllowed( {static_cast<uint64_t>(l_req.addr)&(0x00000000FFFFFFFFull), diff --git a/src/sbefw/core/sbeglobals.H b/src/sbefw/core/sbeglobals.H index e182a20b..9b970a20 100644 --- a/src/sbefw/core/sbeglobals.H +++ b/src/sbefw/core/sbeglobals.H @@ -36,7 +36,7 @@ #define SBE_GLOBAL sbeGlobal constexpr size_t MAX_MAIN_STORE_REGIONS = 8; -constexpr size_t MAX_OCC_SRAM_REGIONS = 2; +constexpr size_t MAX_OCC_SRAM_REGIONS = 1; // Extern declartion, Defined in sbeglobal.C extern uint8_t sbe_Kernel_NCInt_stack[SBE_NONCRITICAL_STACK_SIZE]; diff --git a/src/test/testcases/testSram.py b/src/test/testcases/testSram.py index 1465705e..8e775127 100644 --- a/src/test/testcases/testSram.py +++ b/src/test/testcases/testSram.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016,2017 +# Contributors Listed Below - COPYRIGHT 2016,2018 # [+] International Business Machines Corp. # # @@ -127,20 +127,21 @@ def main( ): testcase = "sec put test 3" putsram(0xFFFBE000-128, 0x01, data, 0x0005, 0x0014) print("Success: "+testcase) - + + # comment out -ve tests for security wisnidw as we allow read always # secure mem - read on disallowed mem # start and end completely outside - testcase = "sec get test 1" - getsram(0xFFFBE000-256, 0x01, 256, 0x0005, 0x0014) - print("Success: "+testcase) + #testcase = "sec get test 1" + #getsram(0xFFFBE000-256, 0x01, 256, 0x0005, 0x0014) + #print("Success: "+testcase) # start outside and end inside the window - testcase = "sec get test 2" - getsram(0xFFFBE000-128, 0x01, 256, 0x0005, 0x0014) - print("Success: "+testcase) + #testcase = "sec get test 2" + #getsram(0xFFFBE000-128, 0x01, 256, 0x0005, 0x0014) + #print("Success: "+testcase) # start inside and end outside the window - testcase = "sec get test 3" - getsram(0xFFFBE000-128, 0x01, 256, 0x0005, 0x0014) - print("Success: "+testcase) + #testcase = "sec get test 3" + #getsram(0xFFFBE000-128, 0x01, 256, 0x0005, 0x0014) + #print("Success: "+testcase) # Put Occ Sram test - Circular - Can be enabled once we get # valid address range to read the circular data |