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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-01-12 16:13:13 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-01-24 01:03:32 -0500 |
| commit | 966af1aea2a8460602a883fbf3db49dad8117d91 (patch) | |
| tree | 8c98acf03180143e9b5e06c732e5846053df389f /src | |
| parent | 7c70e7167c6f033c9711f4fcbe5630a6abf00ab0 (diff) | |
| download | talos-sbe-966af1aea2a8460602a883fbf3db49dad8117d91.tar.gz talos-sbe-966af1aea2a8460602a883fbf3db49dad8117d91.zip | |
FBC updates for HW383616, HW384245
Change-Id: I3b65925b1cadb6f4db5d64868f997ebf4ff7e625
CQ: HW383616
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34810
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34815
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 36 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml | 2 |
2 files changed, 36 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 226b3a8b..b0a88471 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1831,6 +1831,42 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW383616</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 only: enable workaround for HW383616 + Restrict GP/SP high water mark + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW384245</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 only: enable workaround for HW384245 + Restrict TL DOB limit + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <!-- Memory Section --> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 3d560908..339007c0 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -239,7 +239,6 @@ <description> Processor SMP topology configuration. 0 = default = 1 or 2 hop topology (PHYP image spans system) - 1 = 3 hop topology (PHYP image spans group). Provided by the MRW. </description> <valueType>uint8</valueType> @@ -327,7 +326,6 @@ <description> Processor memory map configuration. 0 = default = large system address map - 1 = small system address map Provided by the MRW. </description> <valueType>uint8</valueType> |
