Ring support (Cronus safe): Adding ex_l2/l3_fure_1 to RingID list.

This commit simply adds the rings at the very end of the RingID
  list in p9_ring_id.h in an attempt to not interfere with the
  precompiled built-in version of this header file in Cronus.

Change-Id: I3f7b5db5835688adddf060910a2af88bb9b477ba
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32272
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32277
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 60 insertions, 47 deletions

diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
index 7526b192..65e9db03 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
@@ -357,55 +357,57 @@ const GenRingIdList RING_ID_LIST_COMMON[] =
     {"eq_time"                    , 0x02, 0x10, 0x10, NON_VPD_RING, 0, 0x0C10000000000100},
     {"eq_mode"                    , 0x03, 0x10, 0x10, NON_VPD_RING, 0, 0x0C10000000004000},
     {"ex_l3_fure"                 , 0x04, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000009000},
-    {"ex_l3_gptr"                 , 0x05, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000002000},
-    {"ex_l3_time"                 , 0x06, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000000100},
-    {"ex_l2_mode"                 , 0x07, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000004000},
-    {"ex_l2_fure"                 , 0x08, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000009000},
-    {"ex_l2_gptr"                 , 0x09, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000002000},
-    {"ex_l2_time"                 , 0x0a, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000000100},
-    {"ex_l3_refr_fure"            , 0x0b, 0x10, 0x10, NON_VPD_RING, 0, 0x0008000000009000},
-    {"ex_l3_refr_gptr"            , 0x0c, 0x10, 0x10, NON_VPD_RING, 0, 0x0008000000002000},
-    {"eq_ana_func"                , 0x0d, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000008000},
-    {"eq_ana_gptr"                , 0x0e, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000002000},
-    {"eq_dpll_func"               , 0x0f, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000008000},
-    {"eq_dpll_gptr"               , 0x10, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000002000},
-    {"eq_dpll_mode"               , 0x11, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000004000},
-    {"eq_ana_bndy_bucket_0"       , 0x12, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_1"       , 0x13, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_2"       , 0x14, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_3"       , 0x15, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_4"       , 0x16, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_5"       , 0x17, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_6"       , 0x18, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_7"       , 0x19, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_8"       , 0x1a, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_9"       , 0x1b, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_10"      , 0x1c, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_11"      , 0x1d, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_12"      , 0x1e, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_13"      , 0x1f, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_14"      , 0x20, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_15"      , 0x21, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_16"      , 0x22, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_17"      , 0x23, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_18"      , 0x24, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_19"      , 0x25, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_20"      , 0x26, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_21"      , 0x27, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_22"      , 0x28, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_23"      , 0x29, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_24"      , 0x2a, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_bucket_25"      , 0x2b, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_bndy_l3dcc_bucket_26", 0x2c, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
-    {"eq_ana_mode"                , 0x2d, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000004000},
+    {"ex_l3_fure_1"               , 0x05, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000009000},
+    {"ex_l3_gptr"                 , 0x06, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000002000},
+    {"ex_l3_time"                 , 0x07, 0x10, 0x10, NON_VPD_RING, 0, 0x0200000000000100},
+    {"ex_l2_mode"                 , 0x08, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000004000},
+    {"ex_l2_fure"                 , 0x09, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000009000},
+    {"ex_l2_fure_1"               , 0x0a, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000009000},
+    {"ex_l2_gptr"                 , 0x0b, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000002000},
+    {"ex_l2_time"                 , 0x0c, 0x10, 0x10, NON_VPD_RING, 0, 0x0080000000000100},
+    {"ex_l3_refr_fure"            , 0x0d, 0x10, 0x10, NON_VPD_RING, 0, 0x0008000000009000},
+    {"ex_l3_refr_gptr"            , 0x0e, 0x10, 0x10, NON_VPD_RING, 0, 0x0008000000002000},
+    {"eq_ana_func"                , 0x0f, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000008000},
+    {"eq_ana_gptr"                , 0x10, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000002000},
+    {"eq_dpll_func"               , 0x11, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000008000},
+    {"eq_dpll_gptr"               , 0x12, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000002000},
+    {"eq_dpll_mode"               , 0x13, 0x10, 0x10, NON_VPD_RING, 0, 0x0002000000004000},
+    {"eq_ana_bndy_bucket_0"       , 0x14, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_1"       , 0x15, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_2"       , 0x16, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_3"       , 0x17, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_4"       , 0x18, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_5"       , 0x19, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_6"       , 0x1a, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_7"       , 0x1b, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_8"       , 0x1c, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_9"       , 0x1d, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_10"      , 0x1e, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_11"      , 0x1f, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_12"      , 0x20, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_13"      , 0x21, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_14"      , 0x22, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_15"      , 0x23, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_16"      , 0x24, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_17"      , 0x25, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_18"      , 0x26, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_19"      , 0x27, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_20"      , 0x28, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_21"      , 0x29, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_22"      , 0x2a, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_23"      , 0x2b, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_24"      , 0x2c, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_bucket_25"      , 0x2d, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_bndy_l3dcc_bucket_26", 0x2e, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000000080},
+    {"eq_ana_mode"                , 0x2f, 0x10, 0x10, NON_VPD_RING, 0, 0x0020000000004000},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"eq_repr"          , 0x2e, 0x10, 0x1b, NON_VPD_RING, 0, 0x0C10000000000200},
-    {"ex_l3_repr"       , 0x2f, 0x10, 0x1b, NON_VPD_RING, 0, 0x0200000000000200},
-    {"ex_l2_repr"       , 0x30, 0x10, 0x1b, NON_VPD_RING, 0, 0x0080000000000200},
-    {"ex_l3_refr_repr"  , 0x31, 0x10, 0x1b, NON_VPD_RING, 0, 0x0008000000000200},
-    {"ex_l3_refr_time"  , 0x32, 0x10, 0x1b, NON_VPD_RING, 0, 0x0008000000000100},
+    {"eq_repr"          , 0x30, 0x10, 0x1b, NON_VPD_RING, 0, 0x0C10000000000200},
+    {"ex_l3_repr"       , 0x31, 0x10, 0x1b, NON_VPD_RING, 0, 0x0200000000000200},
+    {"ex_l2_repr"       , 0x32, 0x10, 0x1b, NON_VPD_RING, 0, 0x0080000000000200},
+    {"ex_l3_refr_repr"  , 0x33, 0x10, 0x1b, NON_VPD_RING, 0, 0x0008000000000200},
+    {"ex_l3_refr_time"  , 0x34, 0x10, 0x1b, NON_VPD_RING, 0, 0x0008000000000100},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, CC, RL};
 };
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
index 7db34416..4bda700e 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
@@ -762,6 +762,8 @@ enum RingOffset
     eq_ana_bndy_bucket_25  = 43,
     eq_ana_bndy_l3dcc_bucket_26  = 44,
     eq_ana_mode     = 45,
+    ex_l2_fure_1    = 46,
+    ex_l3_fure_1    = 47,
     // Instance Rings
     eq_repr         = (0 | INSTANCE_RING_MARK),
     ex_l3_repr      = (1 | INSTANCE_RING_MARK),
@@ -773,7 +775,7 @@ enum RingOffset
 static const CHIPLET_DATA g_eqData =
 {
     16, // Quad Chiplet ID range is 16 - 21. The base ID is 16.
-    46, // 46 common rings for Quad chiplet.
+    48, // 48 common rings for Quad chiplet.
     5,  // 5 instance specific rings for each EQ chiplet
     9   // 9 different rings since 2 per EX ring and 1 per EQ
 };
@@ -1060,6 +1062,8 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EC::ec_time                        , "ec_time"                     , EC_TYPE    }, // 226
     { EC::ec_mode                        , "ec_mode"                     , EC_TYPE    }, // 227
     { EC::ec_repr                        , "ec_repr"                     , EC_TYPE    }, // 228
+    { EQ::ex_l2_fure_1                   , "ex_l2_fure_1"                , EQ_TYPE    }, // 229
+    { EQ::ex_l3_fure_1                   , "ex_l3_fure_1"                , EQ_TYPE    }, // 230
 };
 #endif
 #ifdef __PPE__
@@ -1294,6 +1298,8 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EC::ec_time                        , EC_TYPE    }, // 226
     { EC::ec_mode                        , EC_TYPE    }, // 227
     { EC::ec_repr                        , EC_TYPE    }, // 228
+    { EQ::ex_l2_fure_1                   , EQ_TYPE    }, // 229
+    { EQ::ex_l3_fure_1                   , EQ_TYPE    }, // 230
 };
 #endif
 
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
index 90ff5493..c4ec706b 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
+++ b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
@@ -319,6 +319,11 @@ enum RingID
     // Core Chiplet Rings
     // EC0 - EC23 instance specific Ring
     ec_repr = 228,
+
+    // Additional rings
+    ex_l2_fure_1 = 229,
+    ex_l3_fure_1 = 230,
+
     //***************************
     // Rings needed for SBE - End
     //***************************