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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-10-02 11:40:49 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-10-05 07:29:29 -0500 |
| commit | 6ef77d03b31f971caa3be474e101c132351977d1 (patch) | |
| tree | 923b1d22d8499cea119b7dfb598202e4e4ac1613 /src | |
| parent | 74de67ab50906c4a7178210308326c4480655553 (diff) | |
| download | talos-sbe-6ef77d03b31f971caa3be474e101c132351977d1.tar.gz talos-sbe-6ef77d03b31f971caa3be474e101c132351977d1.zip | |
whitelist updates for ABUS CCM
in recovery flow, write access required to:
- reset RX lane control registers
- reset captured link errors
Change-Id: Ifcee8ac86c390aae2d474daedce03e07e198f45b
CQ: SW447360
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66890
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66894
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/security/p9_security_white_black_list.csv | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/import/chips/p9/security/p9_security_white_black_list.csv b/src/import/chips/p9/security/p9_security_white_black_list.csv index 9ae1246a..91dbf001 100644 --- a/src/import/chips/p9/security/p9_security_white_black_list.csv +++ b/src/import/chips/p9/security/p9_security_white_black_list.csv @@ -206,6 +206,10 @@ Version,Chiplet,Base Address,Chiplet Id - range,Bit Mask,User,Register Name,Desc ,OBUS,000000000901080F,0x09-0x0C,,HWSV,PowerBus OLL Optical Config register,,write_whitelist, ,OBUS,0000000009010810,0x09-0x0C,,HWSV,PowerBus OLL TX0 Lane Control register,,write_whitelist, ,OBUS,0000000009010811,0x09-0x0C,,HWSV,PowerBus OLL TX1 Lane Control register,,write_whitelist, +,OBUS,0000000009010812,0x09-0x0C,,HWSV,PowerBus OLL RX0 Lane Control register,,write_whitelist, +,OBUS,0000000009010813,0x09-0x0C,,HWSV,PowerBus OLL RX1 Lane Control register,,write_whitelist, +,OBUS,0000000009010816,0x09-0x0C,,HWSV,PowerBus OLL Link0 Error Status register,,write_whitelist, +,OBUS,0000000009010817,0x09-0x0C,,HWSV,PowerBus OLL Link1 Error Status register,,write_whitelist, ,OBUS,000000000901081A,0x09-0x0C,,HWSV,PowerBus OLL Retrain Threshold register,,write_whitelist, ,OBUS,0000000009011050,0x09-0x0C,,HWSV,PPE External Interface XCR register,,write_whitelist, ,OBUS,8000080009010C3F,0x09-0x0C,,HWSV,rx(tx)_lane_ana_pdwn rx_lane_dig_pdwn and rx_lane_disabled,,write_whitelist, |
