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author | Joe McGill <jmcgill@us.ibm.com> | 2017-11-25 11:59:18 -0600 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-11-28 10:30:48 -0500 |
commit | 5888fd570b00c3eabf07578f5ae6c16344472ec3 (patch) | |
tree | 52805ae45c6937d480e0597648a5a1b4986b2455 /src | |
parent | 5c10f8ace1fc3946274d494c9bdd7076a426f4fa (diff) | |
download | talos-sbe-5888fd570b00c3eabf07578f5ae6c16344472ec3.tar.gz talos-sbe-5888fd570b00c3eabf07578f5ae6c16344472ec3.zip |
remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstate
p9_sbe_chiplet_reset
remove deassertion of OBUS clk async reset, shift to
p9_sbe_startclock_chiplets
p9_sbe_startclock_chiplets
conditionally remove workaround (assert iovalid, clock, deassert iovalid)
instituted to flush DL glmux select pipeline, these will be set via scan
for supported chips
deassert OBUS clk async reset
p9_chiplet_scominit
remove assertion of NV iovalid from HB
p9.npu.scan.initfile
alter flush state of NVDL glsmux select pipe latches to 0b10
p9.obus.scan.initfile
alter flush state of IOO PHY logic to enable lane clocks
clear RX_LANE_ANA_PDWN
clear RX_CLKDIST_PDWN
set RX_IREF_PDWN_B
Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657
CQ: HW404391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50029
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
4 files changed, 111 insertions, 41 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index faac257b..db977093 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -346,18 +346,6 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const for (auto& targ : l_perv_func) { - // OBUS - uint32_t l_chipletID = targ.getChipletNumber(); - - if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) - { - FAPI_DBG("Drop clk async reset for N3, Mc and Obus chiplets"); - FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ)); - } - } - - for (auto& targ : l_perv_func) - { //MC uint32_t l_chipletID = targ.getChipletNumber(); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C index d522b811..6b42814f 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -66,6 +66,9 @@ static fapi2::ReturnCode p9_sbe_startclock_chiplets_meshctrl_setup( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, const bool value); +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, const uint8_t i_attr); @@ -91,6 +94,7 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const fapi2::buffer<uint8_t> l_attr_obus_ratio; fapi2::buffer<uint16_t> l_attr_pg; bool l_obus_chiplets = false; + uint8_t l_hw404391_scom = false; FAPI_DBG("p9_sbe_startclock_chiplets: Entering ..."); @@ -105,6 +109,9 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, l_attr_obus_ratio)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW404391_SCOM, i_target_chip, + l_hw404391_scom)); + FAPI_TRY(p9_sbe_common_get_pg_vector(i_target_chip, l_pg_vector)); FAPI_DBG("partial good targets vector: %#018lX", l_pg_vector); @@ -156,39 +163,44 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const // OBUS if(l_obus_chiplets) { - - FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(targ, REGION1_PBIOOA, l_regions)); - FAPI_DBG("Regions value: %#018lX", l_regions); - - FAPI_DBG("Set nv2 iovalid"); - l_data64.flush<0>(); - l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_6D>(); - l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_7D>(); - l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_8D>(); - FAPI_TRY(fapi2::putScom(targ, PERV_CPLT_CONF1_OR, l_data64)); - - FAPI_DBG("drop chiplet fence for OB"); - FAPI_TRY(p9_sbe_startclock_chiplets_fence_drop(targ)); - - FAPI_DBG("Clock start : region 1 pbiooa to propagate the clock select for nv logic"); - FAPI_TRY(p9_sbe_common_clock_start_stop(targ, CLOCK_CMD_START, - DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); - - FAPI_DBG("Clock stop : region 1 pbiooa "); - FAPI_TRY(p9_sbe_common_clock_start_stop(targ, CLOCK_CMD_STOP, - DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); - - FAPI_DBG("raise chiplet fence for OB"); - l_data_cplt_fence.flush<0>(); - l_data_cplt_fence.setBit<PERV_1_NET_CTRL0_FENCE_EN>(); - FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR, l_data_cplt_fence)); - - FAPI_DBG("Clear nv2 iovalid"); - FAPI_TRY(fapi2::putScom(targ, PERV_CPLT_CONF1_CLEAR, l_data64)); + if (l_hw404391_scom) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(targ, REGION1_PBIOOA, l_regions)); + FAPI_DBG("Regions value: %#018lX", l_regions); + + FAPI_DBG("Set nv2 iovalid"); + l_data64.flush<0>(); + l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_6D>(); + l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_7D>(); + l_data64.setBit<PERV_1_CPLT_CONF1_IOVALID_8D>(); + FAPI_TRY(fapi2::putScom(targ, PERV_CPLT_CONF1_OR, l_data64)); + + FAPI_DBG("drop chiplet fence for OB"); + FAPI_TRY(p9_sbe_startclock_chiplets_fence_drop(targ)); + + FAPI_DBG("Clock start : region 1 pbiooa to propagate the clock select for nv logic"); + FAPI_TRY(p9_sbe_common_clock_start_stop(targ, CLOCK_CMD_START, + DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); + + FAPI_DBG("Clock stop : region 1 pbiooa "); + FAPI_TRY(p9_sbe_common_clock_start_stop(targ, CLOCK_CMD_STOP, + DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); + + FAPI_DBG("raise chiplet fence for OB"); + l_data_cplt_fence.flush<0>(); + l_data_cplt_fence.setBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR, l_data_cplt_fence)); + + FAPI_DBG("Clear nv2 iovalid"); + FAPI_TRY(fapi2::putScom(targ, PERV_CPLT_CONF1_CLEAR, l_data64)); + } FAPI_DBG("Meshctrl setup"); FAPI_TRY(p9_sbe_startclock_chiplets_meshctrl_setup(targ, ((l_ndl_meshctrl_setup >> (12 - l_chipletID)) & 1))); + FAPI_DBG("Drop clk async reset for Obus chiplets"); + FAPI_TRY(p9_sbe_startclock_chiplets_ob_async_reset(targ)); + FAPI_DBG("Reset syncclk muxsel for obus chiplets"); FAPI_TRY(p9_sbe_startclock_chiplets_reset_syncclk_muxsel(targ)); @@ -283,6 +295,29 @@ fapi_try_exit: return fapi2::current_err; } +/// @brief Dropping the net_ctrl0 clock_async_reset +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_ob_async_reset: Entering ..."); + + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.CLK_ASYNC_RESET = 0 + l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_startclock_chiplets_ob_async_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + /// @brief set obus ratio /// /// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 94e172bc..5dfe5336 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5671,4 +5671,47 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCAN</id>> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.1+: Workaround glxmux xstate issue by adjusting scan flush + state of selected latches in NVDL and PHY logic + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x21</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404391_SCOM</id>> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD2.0 + Cumulus: Workaround glxmux xstate issue by applying SCOM + sequence + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index ac308682..15de2e47 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -534,6 +534,10 @@ attribute tank <virtual/> </entry> <entry> + <name>ATTR_CHIP_EC_FEATURE_HW404391_SCOM</name> + <virtual/> + </entry> + <entry> <name>ATTR_SBE_ADDR_KEY_STASH_ADDR</name> <value>0x0000000000000000</value> </entry> |