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| author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-09-16 13:30:26 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-09-27 20:52:45 -0500 |
| commit | 5833ebe6d677105b6162f84241d72d15a74c6dbd (patch) | |
| tree | 9beed8676ca718e8bd83694fc1527b96a08402c3 /src | |
| parent | 656d77e999c1edf3b5addafc78119d8cc8b3af4a (diff) | |
| download | talos-sbe-5833ebe6d677105b6162f84241d72d15a74c6dbd.tar.gz talos-sbe-5833ebe6d677105b6162f84241d72d15a74c6dbd.zip | |
STOP:Dont clear pmc_pcb_intr_type0_pending in OISR1/OIMR1 register
Key_Cronus_Test=PM_REGRESS
Change-Id: I71aac7f826b0daa594de5f4db7a45ccd693f964f
CQ:SW444760
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66511
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66519
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C | 41 |
1 files changed, 26 insertions, 15 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C index a0ead5e7..0e1dbc6a 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -138,6 +138,16 @@ const uint64_t OCBLWSBRn[4] = {PU_OCB_OCI_OCBLWSBR0_SCOM, PU_OCB_OCI_OCBLWSBR3_SCOM }; +const uint32_t PU_OCB_OCI_OIMR0_OR = PU_OCB_OCI_OIMR0_SCOM2; +const uint32_t PU_OCB_OCI_OIMR1_OR = PU_OCB_OCI_OIMR1_SCOM2; + +const uint32_t PU_OCB_OCI_OITR0_CLEAR = PU_OCB_OCI_OITR0_SCOM1; +const uint32_t PU_OCB_OCI_OITR1_CLEAR = PU_OCB_OCI_OITR1_SCOM1; +const uint32_t PU_OCB_OCI_OIEPR0_CLEAR = PU_OCB_OCI_OIEPR0_SCOM1; +const uint32_t PU_OCB_OCI_OIEPR1_CLEAR = PU_OCB_OCI_OIEPR1_SCOM1; +const uint32_t PU_OCB_OCI_OISR0_CLEAR = PU_OCB_OCI_OISR0_SCOM1; +const uint32_t PU_OCB_OCI_OISR1_CLEAR = PU_OCB_OCI_OISR1_SCOM1; + //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ @@ -569,53 +579,54 @@ fapi2::ReturnCode pm_ocb_reset( // - keep word1 0's for simics l_buf64.flush<0>().insertFromRight<0, 32>(INTERRUPT_SRC_MASK_REG); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OIMR0_SCOM2, + PU_OCB_OCI_OIMR0_OR, l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Source Mask Register0 (OIMR0)"); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OIMR1_SCOM2, + PU_OCB_OCI_OIMR1_OR, l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Source Mask Register1 (OIMR1)"); // Clear OCC Interrupt Type Registers 0 & 1 + l_buf64.flush<1>(); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OITR0_SCOM2, - 0), + PU_OCB_OCI_OITR0_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Type Register0 (OITR0)"); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OITR1_SCOM2, - 0), + PU_OCB_OCI_OITR1_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Type Register1 (OITR1)"); // Clear OCC Interupt Edge/Polarity Registers 0 & 1 FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OIEPR0_SCOM2, - 0), + PU_OCB_OCI_OIEPR0_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Edge Polarity Register0 (OIEPR0)"); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OIEPR1_SCOM2, - 0), + PU_OCB_OCI_OIEPR1_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Edge Polarity Register1 (OIEPR1)"); // Clear OCC Interrupt Source Registers 0 & 1 FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OISR0_SCOM2, - 0), + PU_OCB_OCI_OISR0_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Source Register0 (OISR0)"); FAPI_TRY(fapi2::putScom(i_target, - PU_OCB_OCI_OISR1_SCOM2, - 0), + PU_OCB_OCI_OISR1_CLEAR, + l_buf64), "**** ERROR : Unexpected error encountered in write to OCC " "Interrupt Source Register1 (OISR1)"); |
