diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2017-03-02 09:47:11 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-31 01:09:58 -0400 |
| commit | 526fcd4e48ebd65ea3ed6ef996794be92c617b0f (patch) | |
| tree | 088752b8578cbc8efb0392e8596d59066fe99b31 /src | |
| parent | 399fecf5280d573ce53712e2e9648b9c9b86e036 (diff) | |
| download | talos-sbe-526fcd4e48ebd65ea3ed6ef996794be92c617b0f.tar.gz talos-sbe-526fcd4e48ebd65ea3ed6ef996794be92c617b0f.zip | |
update DPLL and IVRM inits
create new EQ analog specific scan initfile
shift application of eq_ana_func ring from cache_initf->cache_dpll_initf
adjust DPLL FF slew rate
add EC feature attributes for DD1 controls
Change-Id: I0000927e946f59e29f312dc9d5b5155676bb5d3c
RTC: 170960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37370
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37376
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
3 files changed, 61 insertions, 4 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C index 7467ee53..8ec1d04e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -65,6 +65,10 @@ p9_hcd_cache_dpll_initf( FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func), "Error from putRing (eq_dpll_func)"); + FAPI_DBG("Scan eq_ana_func ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_ana_func), + "Error from putRing (eq_ana_func)"); + fapi_try_exit: FAPI_INF("<<p9_hcd_cache_dpll_initf"); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C index 6dd1f766..503723bf 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C @@ -95,9 +95,6 @@ p9_hcd_cache_initf( FAPI_DBG("Scan eq_fure ring"); FAPI_TRY(fapi2::putRing(i_target, eq_fure), "Error from putRing (eq_fure)"); - FAPI_DBG("Scan eq_ana_func ring"); - FAPI_TRY(fapi2::putRing(i_target, eq_ana_func), - "Error from putRing (eq_ana_func)"); for (auto& l_ex_target : i_target.getChildren<fapi2::TARGET_TYPE_EX>()) { diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 8edca704..d90aa813 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2738,4 +2738,60 @@ <!-- ******************************************************************** --> <!-- End Memory Section --> <!-- ******************************************************************** --> + + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_DD1_ANALOG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 update : Scan init VDM and IVRM latch workarounds. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_DD1_DPLL_SETTINGS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 update : Scan init DPL Jump Values (SCOMMABLE in DD2). True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_POSTDD1N_DPLL_SETTINGS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Post DD1 update : Used for new DD2 settings such as ..._EXTERNAL_JUMP_VALUES latch is new for DD2. True if: + Nimbus EC greater than or equal to 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> </attributes> + |
