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author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-06-08 05:48:31 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-28 22:26:27 -0500 |
commit | 4cdd98c7b58c6a252e68343d2227d989dff0f9f6 (patch) | |
tree | 9e53b701ee57dd5d5e2d68be9dc63f6450ff19f2 /src | |
parent | 29dc73e65524295f14b624fdb86c2f0de5875ad2 (diff) | |
download | talos-sbe-4cdd98c7b58c6a252e68343d2227d989dff0f9f6.tar.gz talos-sbe-4cdd98c7b58c6a252e68343d2227d989dff0f9f6.zip |
PM: Added support for PGPE Boot/PGPE integration
- support for P-State parameter block
- implements a compact image layout of PGPE similar to CME/SGPE.
- adds PGPE boot progress code as a field in PPMR header.
- implements PGPE boot loader and PGPE boot copier.
- incorporates ability to generate PPMR header in the build flow.
- change logic for calculating CME's first block copy length.
- Turned on generated tables in PGPE Hcode
- Fixed up pointers to generated tables
- add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops
- fix p9_pstate_parameter_build bug with AVS timing attributes
- Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR
- Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug
- Fix Endianes issues in OCC PPB and input slope calcs
- Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known.
- Build flag for OCc Immediate IPC response
- Build flag to no use temp boot settings
- Expanding tracing for debug
- Added default values for PBAX attributes as placeholders for MRW in firmware
- Added WOF VFRT structure definions to headers; movement into HOMER NOT
yet supported
- Addressed review comments and rebased
- Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus
Change-Id: I4752debbc7fb3275d4e79804333654511de427ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35200
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml | 10 | ||||
-rw-r--r-- | src/import/chips/p9/xip/p9_xip_image.h | 12 |
2 files changed, 16 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index 3038533b..756bcce6 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -841,9 +841,12 @@ This is matched to pbax_groupid of the PMISC Address phase. Provided by the Machine Readable Workbook. + + Platform default: Nimbus systems = 0 </description> <valueType>uint8</valueType> <platInit/> + <initToZero/> </attribute> <!-- ********************************************************************* --> <attribute> @@ -855,9 +858,12 @@ pbax_type=unicast. Provided by the Machine Readable Workbook. + + Platform default: Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID </description> <valueType>uint8</valueType> <platInit/> + <initToZero/> <!-- This here strictly to allocate the attribute in Cronus --> </attribute> <!-- ********************************************************************* --> <attribute> @@ -869,10 +875,12 @@ bit in this vector at the decoded bit location is a 1, then this receive engine will participate in the broadcast operation. - Provided by the Machine Readable Workbook. + Override attribute. Platform value of 0 indiates the OCC firmware will + perform this function. </description> <valueType>uint8</valueType> <platInit/> + <initToZero/> </attribute> <!-- ********************************************************************* --> <attribute> diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 14143cce..b096c68f 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -1083,7 +1083,7 @@ p9_xip_find(void* i_image, /// /// \retval non-0 See \ref p9_xip_image_errors int -p9_xip_delete_section(void* io_image, +p9_xip_delete_section(void* io_image, void* o_imageBuf, const uint32_t i_imageBufSize, const int i_sectionId); @@ -1893,14 +1893,16 @@ typedef enum typedef enum { - P9_XIP_SECTION_PGPE_LVL1_BL = P9_XIP_SECTIONS_PLUS(0), - P9_XIP_SECTION_PGPE_LVL2_BL = P9_XIP_SECTIONS_PLUS(1), - P9_XIP_SECTION_PGPE_HCODE = P9_XIP_SECTIONS_PLUS(2), - P9_XIP_SECTIONS_PGPE = P9_XIP_SECTIONS_PLUS(3) // # sections + P9_XIP_SECTION_PGPE_PPMR = P9_XIP_SECTIONS_PLUS(0), + P9_XIP_SECTION_PGPE_LVL1_BL = P9_XIP_SECTIONS_PLUS(1), + P9_XIP_SECTION_PGPE_LVL2_BL = P9_XIP_SECTIONS_PLUS(2), + P9_XIP_SECTION_PGPE_HCODE = P9_XIP_SECTIONS_PLUS(3), + P9_XIP_SECTIONS_PGPE = P9_XIP_SECTIONS_PLUS(4) // # sections } p9_xip_section_pgpe_t; #define P9_XIP_SECTION_NAMES_PGPE(var) \ P9_XIP_SECTION_NAMES(var, \ + ".ppmr_header", \ ".lvl1_bl", \ ".lvl2_bl", \ ".hcode") |