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| author | Yue Du <daviddu@us.ibm.com> | 2017-03-01 22:15:29 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-31 01:10:59 -0400 |
| commit | 41771befe68b8042ff6e1ec5a852a5e29b447166 (patch) | |
| tree | 74665291c19c707bd4f160910eb278f860dca15e /src | |
| parent | 2dced3fcc7d092108c0df39a93aee9c8aa116ffb (diff) | |
| download | talos-sbe-41771befe68b8042ff6e1ec5a852a5e29b447166.tar.gz talos-sbe-41771befe68b8042ff6e1ec5a852a5e29b447166.zip | |
HW404292: Assert analog fence in cache_chiplet_reset
Change-Id: I610042d0802e80ec53255f38cfc27cd8d9660305
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37320
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37372
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
3 files changed, 10 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C index f4585e5a..d6ca2efe 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -106,8 +106,11 @@ p9_hcd_cache_dpll_setup( // Prepare to start DPLL clock //---------------------------- + FAPI_DBG("Drop analog logic fence via QPPM_PFCS[11]"); + FAPI_TRY(putScom(i_target, EQ_PPM_PFCS_WCLEAR, MASK_SET(11))); + FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]"); - l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x40); + l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x01); FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64)); FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C index f1424fc5..7478dd8a 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -103,6 +103,9 @@ p9_hcd_cache_poweron( FAPI_DBG("Assert cache glsmux reset via CLOCK_GRID_CTRL[0]"); FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(0))); + FAPI_DBG("Assert analog logic fence via QPPM_PFCS[11]"); + FAPI_TRY(putScom(i_target, EQ_PPM_PFCS_WOR, MASK_SET(11))); + //----------------------- // Power on cache chiplet //----------------------- diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index 9e61d4c4..20cb27dc 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -274,6 +274,8 @@ enum SLAVE_CONFIG_DEFS /// Scom addresses missing from p9_quad_scom_addresses.H #define PU_OCB_OCI_QSSR_CLEAR PU_OCB_OCI_QSSR_SCOM1 #define PU_OCB_OCI_QSSR_OR PU_OCB_OCI_QSSR_SCOM2 +#define EQ_PPM_PFCS_WCLEAR EQ_PPM_PFCS_SCOM1 +#define EQ_PPM_PFCS_WOR EQ_PPM_PFCS_SCOM2 #define EQ_QPPM_QCCR_WCLEAR EQ_QPPM_QCCR_SCOM1 #define EQ_QPPM_QCCR_WOR EQ_QPPM_QCCR_SCOM2 #define EX_0_CME_SCOM_SICR_CLEAR EX_0_CME_SCOM_SICR_SCOM1 |
