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| author | Stephen Glancy <sglancy@us.ibm.com> | 2017-04-12 13:45:43 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-04-18 10:58:18 -0400 |
| commit | 3642fee680eecafd93144c740524ef77d8056223 (patch) | |
| tree | 8f1e1c1d45fd373aa3d50eae310575213801895f /src | |
| parent | 26aa533821aa9041ea908355b8b994df7e6682aa (diff) | |
| download | talos-sbe-3642fee680eecafd93144c740524ef77d8056223.tar.gz talos-sbe-3642fee680eecafd93144c740524ef77d8056223.zip | |
Added read ctr bad delay workaround
The workaround finds the median and moves delays below a specified percentage
of this median to be the median value.
Change-Id: I058c61a1e7734771ab31be3f48760030fbf945b5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39178
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39236
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index ae27e58d..ff5cace8 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2700,6 +2700,23 @@ </attribute> <attribute> + <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + In below DD2 Nimbus, a workaround after read centering might need to be run. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + + <attribute> <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
