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| author | Jenny Huynh <jhuynh@us.ibm.com> | 2018-08-29 17:04:51 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-09-12 22:24:02 -0500 |
| commit | 3399fd3edb8100271aaa8ce1a51236f6f38a6d0d (patch) | |
| tree | a84b619941e98f9fbf2b01d656dd976e986ac987 /src | |
| parent | 4a4cf323a8a188871fdaaa0f9ab21cd2eb25e0b4 (diff) | |
| download | talos-sbe-3399fd3edb8100271aaa8ce1a51236f6f38a6d0d.tar.gz talos-sbe-3399fd3edb8100271aaa8ce1a51236f6f38a6d0d.zip | |
SW427193 / HW461448: Enable memory controller wat
Change-Id: I2fc4cf0dda43d4eba543024605c8f358e22e1bae
CQ:SW427193
CQ:HW461448
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65476
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Adam S. Hale <adam.samuel.hale@ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65508
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index d5fc592c..b13dafe6 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -7842,6 +7842,27 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW461448</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Enable MC WAT to hold off incoming commands to the memory controller after + a certain fullness level. Currently configured to hold off for 75 counts + after reaching 16 entries in the write buffers. This will allow existing + entries in queue to make forward progress before commiting more into the + queues. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_SYNC_SS_PLL_SPREAD</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
