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| author | Brian Silver <bsilver@us.ibm.com> | 2016-11-23 13:37:18 -0600 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2016-12-20 05:18:50 -0600 |
| commit | 30c949e89b5fe7f591d7658fd9368f5f674980b5 (patch) | |
| tree | 78b20cbfb55674f59fc54b486ed4877fe038461f /src | |
| parent | 9178db086740ddfbb517e3e03963dd280d87706a (diff) | |
| download | talos-sbe-30c949e89b5fe7f591d7658fd9368f5f674980b5.tar.gz talos-sbe-30c949e89b5fe7f591d7658fd9368f5f674980b5.zip | |
Add Memory Subsystem FIR support
Add FIR.md to memory/docs
Change some PHY workarounds, lab says hold off
Add MC FIR to SBE code
Change-Id: I904079ab84d978637dd2b3e638c90d59395019fd
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33060
Dev-Ready: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33259
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C | 12 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index 79a9b000..85cd02c3 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -84,6 +84,7 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS> fapi2::buffer<uint64_t> l_mcfgp; fapi2::buffer<uint64_t> l_mcmode1; fapi2::buffer<uint64_t> l_mcfirmask_and; + fapi2::buffer<uint64_t> l_mcaction; // MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp), @@ -111,12 +112,23 @@ fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS> FAPI_TRY(fapi2::putScom(i_target, MCS_MCMODE1, l_mcmode1), "Error from putScom (MCS_MCMODE1)"); + // Setup MC FIR + l_mcaction.setBit<MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR>(); + FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRACT1, l_mcaction), + "Error from putScom (MCS_MCFIRACT1)"); + // MCFIRMASK -- unmask command list/channel timeout errors (so a checkstop will // occur if we break cache containment, but hit against the BAR) l_mcfirmask_and.flush<1>(); l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT>(); l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC>(); l_mcfirmask_and.clearBit<MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_POWERBUS_PROTOCOL_ERROR>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_MULTIPLE_BAR>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_INVALID_ADDRESS>(); + FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and), "Error from putScom (MCS_MCFIRMASK_AND)"); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index b8a7a472..60eaff65 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -501,6 +501,23 @@ </attribute> <attribute> + <id>ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + WAT Debug Attention work-around for Nimbus DD1.0 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + + <attribute> <id>ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
