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authorJenny Huynh <jhuynh@us.ibm.com>2016-12-03 13:42:26 -0600
committerspashabk-in <shakeebbk@in.ibm.com>2016-12-20 05:18:48 -0600
commit20bd30af528676a584f11e7f78275cc4428dcec0 (patch)
tree58c1b184cae7f8771c03f4a3cd964d6d2c5ed884 /src
parent880929b7b1c822ae76d4858b371119299a652b9f (diff)
downloadtalos-sbe-20bd30af528676a584f11e7f78275cc4428dcec0.tar.gz
talos-sbe-20bd30af528676a584f11e7f78275cc4428dcec0.zip
Adding in defect HW395947,HW930007 to INT initfiles
Change-Id: Iff8bed55ac363c8bd881fcc06f9cd3cd40261e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: DAVID M. KAUER <dmkauer@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33424 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml73
1 files changed, 72 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index e5be7e30..b8a7a472 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -256,7 +256,7 @@
<id>ATTR_CHIP_EC_FEATURE_HW386013</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- Nimbus DD1 only: enable workarounds for HW386013
+ Nimbus DD1 only: enable workarounds for HW386013 in FBC initfile
pb_cfg_cent_opt3_mode must be configured as an smp to allow vas data
</description>
<chipEcFeature>
@@ -271,6 +271,77 @@
</attribute>
<!-- ******************************************************************** -->
<attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW378025</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Nimbus DD1 only: enable workarounds for HW378025 in INT initfile
+ Shared credits in ATX can only be updated when clockgate is disabled
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW930007</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Nimbus DD1 only: enable workarounds for HW930007 in INT initfile
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW372116</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Nimbus DD1 only: enable workarounds for HW372116 in INT initfile
+ Remote Ld credit in PC should be set to zero to avoid ATX dropped commands
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW395947</id>
+ <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Nimbus DD1 only: enable workarounds for HW395947 in INT initfile
+ Workaround for relaxed write ordering causing SBT entry corruption
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>LESS_THAN</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
+ <attribute>
<id>ATTR_CHIP_EC_FEATURE_PSI_HALF_SPEED</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
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