Level 2 p9_cpu_special_wakeup

- Restructured to deal with individual core, EQ and EQ targets
     This is necessary as compound targets really can't apply to this procedure
     as the registers being addressed for an EX target changes based on Fused
     mode.
- The above moved the main implemented into p9_cpu_special_wakeup_lib
- Removed tracking attributes
- Removed FUSED CORE support
- EX targets will wake-up up to 2 cores within the EX (dependent on
  functionality)
- Added SUET support
- Rebased (2)
- Made HWP attributes writable
- Added HB platform defaults in hb_temp_defaults.xml (but doesn't compile)
- Address Gerrit comments (included Cronus noticed bug)
- Removed some hb_temp attributes to deal with HB Jenkins fails

Change-Id: I84a66b646477627f0178c3c968580ffc435b5300
RTC: 136795
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20850
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21027
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 2710 insertions, 6 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml
index 95cd6a0c..dbfd8e3e 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml
@@ -22,9 +22,9 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
 <!-- proc_pll_ring_attributes.xml -->
 <attributes>
+  <!-- ********************************************************************* -->
   <attribute>
     <id>ATTR_CORE_REPR_RING</id>
     <targetType>TARGET_TYPE_CORE</targetType>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index 27661cf4..5cfec527 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -943,8 +943,8 @@
     </description>
     <initToZero/>
     <valueType>uint8</valueType>
-    <platInit/>
-  </attribute>
+      <platInit/>
+  </attribute>    
   <!-- ********************************************************************* -->
   <attribute>
       <id>ATTR_POUNDV_BUCKET_NUM</id>
@@ -1421,6 +1421,6 @@
     </description>
     <valueType>uint16</valueType>
     <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
+</attribute>
+   <!-- ********************************************************************* -->
 </attributes>
diff --git a/src/import/chips/p9/sw_simulation/chip.act b/src/import/chips/p9/sw_simulation/chip.act
index 1abe32a4..4a397f58 100644
--- a/src/import/chips/p9/sw_simulation/chip.act
+++ b/src/import/chips/p9/sw_simulation/chip.act
@@ -278,6 +278,6 @@ CAUSE_EFFECT CHIPLETS ec {
 CAUSE_EFFECT{
   LABEL=[TOD statem machine is running]
   WATCH=[REG(0x00040022)]
-  CAUSE: TARGET[REG(0x00040022)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x00040022)] OP=[BIT,ON] BIT=[0]
   EFFECT: TARGET=[REG(0x00040024)] OP=[BIT,ON] BIT=[4]
 }
diff --git a/src/import/chips/p9/sw_simulation/powermgmt.act b/src/import/chips/p9/sw_simulation/powermgmt.act
index b0c79dd2..66560f9a 100644
--- a/src/import/chips/p9/sw_simulation/powermgmt.act
+++ b/src/import/chips/p9/sw_simulation/powermgmt.act
@@ -3506,4 +3506,2708 @@ CAUSE_EFFECT {
   WATCH=[REG(0x01010805]
   EFFECT: TARGET=[REG(0x01010803)] OP=[EQUALTO,BUF] DATA=[REG(0x01010805)]
 }
+##
+## Actions for Procedure - p9_sbe_check_master_stop15 and others
+##
+
+CAUSE_EFFECT {
+  LABEL=[SSH_GATED]
+  WATCH=[REG(0x200F0110)]
+  CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0112)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0113)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0114)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[SSH_REQUEST_LEVEL]
+  WATCH=[REG(0x200F0110)]
+  CAUSE: TARGET=[REG(0x200F0110)]  OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0F080000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0F080000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0112)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0F080000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0113)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0F080000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0114)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0F080000 00000000)] DATA=[REG(0x200F0110]
+}
+
+CAUSE_EFFECT {
+  LABEL=[SSH_ACTUAL_LEVEL]
+  WATCH=[REG(0x200F0110)]
+  CAUSE: TARGET=[REG(0x200F0110)]  OP=[AND,BUF,MASK] MASK=[LITERAL(64, 00F40000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 00F40000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0112)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 00F40000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0113)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 00F40000 00000000)] DATA=[REG(0x200F0110]
+  EFFECT: TARGET=[REG(0x200F0114)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 00F40000 00000000)] DATA=[REG(0x200F0110]
+}
+
+##
+## Actions for Procedure - p9_cpu_special_wakeup
+##
+
+
+
+## Core 0 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x200F010A)]
+  CAUSE: TARGET=[REG(0x200F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x200F010B)]
+  CAUSE: TARGET=[REG(0x200F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x200F010C)]
+  CAUSE: TARGET=[REG(0x200F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x200F010D)]
+  CAUSE: TARGET=[REG(0x200F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x200F010A)]
+  CAUSE: TARGET=[REG(0x200F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x200F010B)]
+  CAUSE: TARGET=[REG(0x200F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x200F010C)]
+  CAUSE: TARGET=[REG(0x200F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x200F010D)]
+  CAUSE: TARGET=[REG(0x200F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 0 End
+
+## Core 1 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x210F010A)]
+  CAUSE: TARGET=[REG(0x210F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x210F010B)]
+  CAUSE: TARGET=[REG(0x210F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x210F010C)]
+  CAUSE: TARGET=[REG(0x210F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x210F010D)]
+  CAUSE: TARGET=[REG(0x210F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x210F010A)]
+  CAUSE: TARGET=[REG(0x210F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x210F010B)]
+  CAUSE: TARGET=[REG(0x210F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x210F010C)]
+  CAUSE: TARGET=[REG(0x210F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x210F010D)]
+  CAUSE: TARGET=[REG(0x210F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 1 End
+
+## Core 2 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x220F010A)]
+  CAUSE: TARGET=[REG(0x220F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x220F010B)]
+  CAUSE: TARGET=[REG(0x220F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x220F010C)]
+  CAUSE: TARGET=[REG(0x220F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x220F010D)]
+  CAUSE: TARGET=[REG(0x220F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x220F010A)]
+  CAUSE: TARGET=[REG(0x220F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x220F010B)]
+  CAUSE: TARGET=[REG(0x220F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x220F010C)]
+  CAUSE: TARGET=[REG(0x220F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x220F010D)]
+  CAUSE: TARGET=[REG(0x220F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 2 End
+
+## Core 3 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x230F010A)]
+  CAUSE: TARGET=[REG(0x230F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x230F010B)]
+  CAUSE: TARGET=[REG(0x230F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x230F010C)]
+  CAUSE: TARGET=[REG(0x230F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x230F010D)]
+  CAUSE: TARGET=[REG(0x230F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x230F010A)]
+  CAUSE: TARGET=[REG(0x230F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x230F010B)]
+  CAUSE: TARGET=[REG(0x230F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x230F010C)]
+  CAUSE: TARGET=[REG(0x230F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x230F010D)]
+  CAUSE: TARGET=[REG(0x230F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 3 End
+
+## Core 4 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x240F010A)]
+  CAUSE: TARGET=[REG(0x240F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x240F010B)]
+  CAUSE: TARGET=[REG(0x240F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x240F010C)]
+  CAUSE: TARGET=[REG(0x240F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x240F010D)]
+  CAUSE: TARGET=[REG(0x240F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x240F010A)]
+  CAUSE: TARGET=[REG(0x240F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x240F010B)]
+  CAUSE: TARGET=[REG(0x240F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x240F010C)]
+  CAUSE: TARGET=[REG(0x240F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x240F010D)]
+  CAUSE: TARGET=[REG(0x240F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 4 End
+
+## Core 5 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x250F010A)]
+  CAUSE: TARGET=[REG(0x250F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x250F010B)]
+  CAUSE: TARGET=[REG(0x250F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x250F010C)]
+  CAUSE: TARGET=[REG(0x250F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x250F010D)]
+  CAUSE: TARGET=[REG(0x250F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x250F010A)]
+  CAUSE: TARGET=[REG(0x250F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x250F010B)]
+  CAUSE: TARGET=[REG(0x250F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x250F010C)]
+  CAUSE: TARGET=[REG(0x250F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x250F010D)]
+  CAUSE: TARGET=[REG(0x250F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 5 End
+
+## Core 6 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x260F010A)]
+  CAUSE: TARGET=[REG(0x260F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x260F010B)]
+  CAUSE: TARGET=[REG(0x260F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x260F010C)]
+  CAUSE: TARGET=[REG(0x260F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x260F010D)]
+  CAUSE: TARGET=[REG(0x260F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x260F010A)]
+  CAUSE: TARGET=[REG(0x260F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x260F010B)]
+  CAUSE: TARGET=[REG(0x260F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x260F010C)]
+  CAUSE: TARGET=[REG(0x260F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x260F010D)]
+  CAUSE: TARGET=[REG(0x260F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 6 End
+
+## Core 7 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x270F010A)]
+  CAUSE: TARGET=[REG(0x270F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x270F010B)]
+  CAUSE: TARGET=[REG(0x270F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x270F010C)]
+  CAUSE: TARGET=[REG(0x270F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x270F010D)]
+  CAUSE: TARGET=[REG(0x270F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x270F010A)]
+  CAUSE: TARGET=[REG(0x270F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x270F010B)]
+  CAUSE: TARGET=[REG(0x270F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x270F010C)]
+  CAUSE: TARGET=[REG(0x270F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x270F010D)]
+  CAUSE: TARGET=[REG(0x270F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 7 End
+
+## Core 8 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x280F010A)]
+  CAUSE: TARGET=[REG(0x280F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x280F010B)]
+  CAUSE: TARGET=[REG(0x280F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x280F010C)]
+  CAUSE: TARGET=[REG(0x280F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x280F010D)]
+  CAUSE: TARGET=[REG(0x280F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x280F010A)]
+  CAUSE: TARGET=[REG(0x280F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x280F010B)]
+  CAUSE: TARGET=[REG(0x280F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x280F010C)]
+  CAUSE: TARGET=[REG(0x280F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x280F010D)]
+  CAUSE: TARGET=[REG(0x280F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 8 End
+
+## Core 9 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x290F010A)]
+  CAUSE: TARGET=[REG(0x290F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x290F010B)]
+  CAUSE: TARGET=[REG(0x290F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x290F010C)]
+  CAUSE: TARGET=[REG(0x290F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x290F010D)]
+  CAUSE: TARGET=[REG(0x290F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x290F010A)]
+  CAUSE: TARGET=[REG(0x290F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x290F010B)]
+  CAUSE: TARGET=[REG(0x290F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x290F010C)]
+  CAUSE: TARGET=[REG(0x290F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x290F010D)]
+  CAUSE: TARGET=[REG(0x290F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 9 End
+
+## Core 10 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2a0F010A)]
+  CAUSE: TARGET=[REG(0x2a0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2a0F010B)]
+  CAUSE: TARGET=[REG(0x2a0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2a0F010C)]
+  CAUSE: TARGET=[REG(0x2a0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2a0F010D)]
+  CAUSE: TARGET=[REG(0x2a0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2a0F010A)]
+  CAUSE: TARGET=[REG(0x2a0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2a0F010B)]
+  CAUSE: TARGET=[REG(0x2a0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2a0F010C)]
+  CAUSE: TARGET=[REG(0x2a0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2a0F010D)]
+  CAUSE: TARGET=[REG(0x2a0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2a0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 10 End
+
+## Core 11 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2b0F010A)]
+  CAUSE: TARGET=[REG(0x2b0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2b0F010B)]
+  CAUSE: TARGET=[REG(0x2b0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2b0F010C)]
+  CAUSE: TARGET=[REG(0x2b0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2b0F010D)]
+  CAUSE: TARGET=[REG(0x2b0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2b0F010A)]
+  CAUSE: TARGET=[REG(0x2b0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2b0F010B)]
+  CAUSE: TARGET=[REG(0x2b0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2b0F010C)]
+  CAUSE: TARGET=[REG(0x2b0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2b0F010D)]
+  CAUSE: TARGET=[REG(0x2b0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2b0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 11 End
+
+## Core 12 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2c0F010A)]
+  CAUSE: TARGET=[REG(0x2c0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2c0F010B)]
+  CAUSE: TARGET=[REG(0x2c0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2c0F010C)]
+  CAUSE: TARGET=[REG(0x2c0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2c0F010D)]
+  CAUSE: TARGET=[REG(0x2c0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2c0F010A)]
+  CAUSE: TARGET=[REG(0x2c0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2c0F010B)]
+  CAUSE: TARGET=[REG(0x2c0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2c0F010C)]
+  CAUSE: TARGET=[REG(0x2c0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2c0F010D)]
+  CAUSE: TARGET=[REG(0x2c0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2c0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 12 End
+
+## Core 13 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2d0F010A)]
+  CAUSE: TARGET=[REG(0x2d0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2d0F010B)]
+  CAUSE: TARGET=[REG(0x2d0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2d0F010C)]
+  CAUSE: TARGET=[REG(0x2d0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2d0F010D)]
+  CAUSE: TARGET=[REG(0x2d0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2d0F010A)]
+  CAUSE: TARGET=[REG(0x2d0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2d0F010B)]
+  CAUSE: TARGET=[REG(0x2d0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2d0F010C)]
+  CAUSE: TARGET=[REG(0x2d0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2d0F010D)]
+  CAUSE: TARGET=[REG(0x2d0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2d0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 13 End
+
+## Core 14 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2e0F010A)]
+  CAUSE: TARGET=[REG(0x2e0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2e0F010B)]
+  CAUSE: TARGET=[REG(0x2e0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2e0F010C)]
+  CAUSE: TARGET=[REG(0x2e0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2e0F010D)]
+  CAUSE: TARGET=[REG(0x2e0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2e0F010A)]
+  CAUSE: TARGET=[REG(0x2e0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2e0F010B)]
+  CAUSE: TARGET=[REG(0x2e0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2e0F010C)]
+  CAUSE: TARGET=[REG(0x2e0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2e0F010D)]
+  CAUSE: TARGET=[REG(0x2e0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2e0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 14 End
+
+## Core 15 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x2f0F010A)]
+  CAUSE: TARGET=[REG(0x2f0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x2f0F010B)]
+  CAUSE: TARGET=[REG(0x2f0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x2f0F010C)]
+  CAUSE: TARGET=[REG(0x2f0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x2f0F010D)]
+  CAUSE: TARGET=[REG(0x2f0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x2f0F010A)]
+  CAUSE: TARGET=[REG(0x2f0F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x2f0F010B)]
+  CAUSE: TARGET=[REG(0x2f0F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x2f0F010C)]
+  CAUSE: TARGET=[REG(0x2f0F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x2f0F010D)]
+  CAUSE: TARGET=[REG(0x2f0F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x2f0F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 15 End
+
+## Core 16 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x300F010A)]
+  CAUSE: TARGET=[REG(0x300F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x300F010B)]
+  CAUSE: TARGET=[REG(0x300F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x300F010C)]
+  CAUSE: TARGET=[REG(0x300F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x300F010D)]
+  CAUSE: TARGET=[REG(0x300F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x300F010A)]
+  CAUSE: TARGET=[REG(0x300F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x300F010B)]
+  CAUSE: TARGET=[REG(0x300F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x300F010C)]
+  CAUSE: TARGET=[REG(0x300F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x300F010D)]
+  CAUSE: TARGET=[REG(0x300F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 16 End
+
+## Core 17 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x310F010A)]
+  CAUSE: TARGET=[REG(0x310F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x310F010B)]
+  CAUSE: TARGET=[REG(0x310F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x310F010C)]
+  CAUSE: TARGET=[REG(0x310F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x310F010D)]
+  CAUSE: TARGET=[REG(0x310F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x310F010A)]
+  CAUSE: TARGET=[REG(0x310F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x310F010B)]
+  CAUSE: TARGET=[REG(0x310F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x310F010C)]
+  CAUSE: TARGET=[REG(0x310F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x310F010D)]
+  CAUSE: TARGET=[REG(0x310F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 17 End
+
+## Core 18 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x320F010A)]
+  CAUSE: TARGET=[REG(0x320F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x320F010B)]
+  CAUSE: TARGET=[REG(0x320F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x320F010C)]
+  CAUSE: TARGET=[REG(0x320F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x320F010D)]
+  CAUSE: TARGET=[REG(0x320F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x320F010A)]
+  CAUSE: TARGET=[REG(0x320F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x320F010B)]
+  CAUSE: TARGET=[REG(0x320F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x320F010C)]
+  CAUSE: TARGET=[REG(0x320F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x320F010D)]
+  CAUSE: TARGET=[REG(0x320F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 18 End
+
+## Core 19 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x330F010A)]
+  CAUSE: TARGET=[REG(0x330F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x330F010B)]
+  CAUSE: TARGET=[REG(0x330F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x330F010C)]
+  CAUSE: TARGET=[REG(0x330F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x330F010D)]
+  CAUSE: TARGET=[REG(0x330F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x330F010A)]
+  CAUSE: TARGET=[REG(0x330F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x330F010B)]
+  CAUSE: TARGET=[REG(0x330F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x330F010C)]
+  CAUSE: TARGET=[REG(0x330F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x330F010D)]
+  CAUSE: TARGET=[REG(0x330F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 19 End
+
+## Core 20 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x340F010A)]
+  CAUSE: TARGET=[REG(0x340F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x340F010B)]
+  CAUSE: TARGET=[REG(0x340F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x340F010C)]
+  CAUSE: TARGET=[REG(0x340F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x340F010D)]
+  CAUSE: TARGET=[REG(0x340F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x340F010A)]
+  CAUSE: TARGET=[REG(0x340F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x340F010B)]
+  CAUSE: TARGET=[REG(0x340F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x340F010C)]
+  CAUSE: TARGET=[REG(0x340F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x340F010D)]
+  CAUSE: TARGET=[REG(0x340F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 20 End
+
+## Core 21 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x350F010A)]
+  CAUSE: TARGET=[REG(0x350F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x350F010B)]
+  CAUSE: TARGET=[REG(0x350F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x350F010C)]
+  CAUSE: TARGET=[REG(0x350F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x350F010D)]
+  CAUSE: TARGET=[REG(0x350F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x350F010A)]
+  CAUSE: TARGET=[REG(0x350F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x350F010B)]
+  CAUSE: TARGET=[REG(0x350F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x350F010C)]
+  CAUSE: TARGET=[REG(0x350F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x350F010D)]
+  CAUSE: TARGET=[REG(0x350F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 21 End
+
+## Core 22 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x360F010A)]
+  CAUSE: TARGET=[REG(0x360F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x360F010B)]
+  CAUSE: TARGET=[REG(0x360F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x360F010C)]
+  CAUSE: TARGET=[REG(0x360F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x360F010D)]
+  CAUSE: TARGET=[REG(0x360F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x360F010A)]
+  CAUSE: TARGET=[REG(0x360F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x360F010B)]
+  CAUSE: TARGET=[REG(0x360F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x360F010C)]
+  CAUSE: TARGET=[REG(0x360F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x360F010D)]
+  CAUSE: TARGET=[REG(0x360F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 22 End
+
+## Core 23 Start
+# Assert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OTR]
+  WATCH=[REG(0x370F010A)]
+  CAUSE: TARGET=[REG(0x370F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_FSP]
+  WATCH=[REG(0x370F010B)]
+  CAUSE: TARGET=[REG(0x370F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_OCC]
+  WATCH=[REG(0x370F010C)]
+  CAUSE: TARGET=[REG(0x370F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_ASSERT_HYP]
+  WATCH=[REG(0x370F010D)]
+  CAUSE: TARGET=[REG(0x370F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 80000000 00000000)]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  #suet CORE_SPWKP_ASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+}
+
+# Deassert actions
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEDEASSERT_OTR]
+  WATCH=[REG(0x370F010A)]
+  CAUSE: TARGET=[REG(0x370F010A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OTR_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_FSP]
+  WATCH=[REG(0x370F010B)]
+  CAUSE: TARGET=[REG(0x370F010B)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_FSP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_OCC]
+  WATCH=[REG(0x370F010C)]
+  CAUSE: TARGET=[REG(0x370F010C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_OCC_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CORE_SPWKP_DEASSERT_HYP]
+  WATCH=[REG(0x370F010D)]
+  CAUSE: TARGET=[REG(0x370F010D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,ON] BIT=[0]
+  #suet CORE_SPWKP_DEASSERT_HYP_TIMEOUT:tc1- EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,ON] BIT=[1]
+  # GPMMR special wakeup done, special wakeup active
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0100)] OP=[BIT,OFF] BIT=[1]
+  # History reg special wakeup done
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[BIT,OFF] BIT=[1]
+}
+
+## Core 23 End
+>>>>>>> Level 2 p9_cpu_special_wakeup