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authorJoe McGill <jmcgill@us.ibm.com>2017-10-27 18:48:39 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2018-01-12 12:04:47 -0500
commit86ae83c5d6a45b3eb616af87adf081f0216fae08 (patch)
treed931207d46e91e3593179fbe5207a7223aedcb8a /src
parent584ee233b010e8c066282951bb97768b072f705a (diff)
downloadtalos-sbe-86ae83c5d6a45b3eb616af87adf081f0216fae08.tar.gz
talos-sbe-86ae83c5d6a45b3eb616af87adf081f0216fae08.zip
MCD disable workaround for HW423589 (option1)
chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 cmvc-prereq: 1043014 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C26
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C20
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml26
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml6
4 files changed, 73 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index f3f27b2b..e9dea042 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2017 */
+/* Contributors Listed Below - COPYRIGHT 2016,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -122,6 +122,30 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
l_scom_buffer.insert<8, 3, 61, uint64_t>(literal_0x3 );
}
+ if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) )
+ {
+ constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON = 0x1;
+ l_scom_buffer.insert<1, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_GROUP_ON );
+ }
+
+ if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) )
+ {
+ constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON = 0x1;
+ l_scom_buffer.insert<5, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_GROUP_ON );
+ }
+
+ if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) )
+ {
+ constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON = 0x1;
+ l_scom_buffer.insert<2, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_WR_DISABLE_VG_NOT_SYS_ON );
+ }
+
+ if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) )
+ {
+ constexpr auto l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON = 0x1;
+ l_scom_buffer.insert<6, 1, 63, uint64_t>(l_NMMU_MM_FBC_CQ_WRAP_NXCQ_SCOM_DMA_RD_DISABLE_VG_NOT_SYS_ON );
+ }
+
FAPI_TRY(fapi2::putScom(TGT0, 0x5012c15ull, l_scom_buffer));
}
{
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index 49a12b75..0281bd9c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2017 */
+/* Contributors Listed Below - COPYRIGHT 2015,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -279,9 +279,25 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
"Error from putScom (PU_PB_EAST_FIR_MASK_REG)");
}
- // configure PBA FIRs
+ // configure PBA mode switches & FIRs
{
fapi2::buffer<uint64_t> l_scom_data;
+ uint8_t l_hw423589_option1;
+
+ // set PBACFG
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION1,
+ i_target,
+ l_hw423589_option1));
+ l_scom_data = 0;
+
+ if (l_hw423589_option1)
+ {
+ l_scom_data.setBit<PU_PBACFG_CHSW_DIS_GROUP_SCOPE>();
+ }
+
+ FAPI_DBG("Resetting PBACFG with value = 0x%16llX", uint64_t(l_scom_data));
+ FAPI_TRY(fapi2::putScom(i_target, PU_PBACFG, l_scom_data),
+ "Error from putScom (PU_PBACFG)");
// clear FIR
FAPI_DBG("Configuring PBA FIR");
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index cd7a4900..19cbe8a1 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
-<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
@@ -5990,4 +5990,28 @@
</chipEcFeature>
</attribute>
<!-- ******************************************************************** -->
+ <attribute>
+ <id>ATTR_CHIP_EC_FEATURE_HW423589_OPTION1</id>
+ <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType>
+ <description>
+ Disable MCD to workaround coherency issue HW423589
+ </description>
+ <chipEcFeature>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x20</value>
+ <test>EQUAL</test>
+ </ec>
+ </chip>
+ <chip>
+ <name>ENUM_ATTR_NAME_NIMBUS</name>
+ <ec>
+ <value>0x22</value>
+ <test>GREATER_THAN_OR_EQUAL</test>
+ </ec>
+ </chip>
+ </chipEcFeature>
+ </attribute>
+ <!-- ******************************************************************** -->
</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 353d183e..08e555f5 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
-<!-- Contributors Listed Below - COPYRIGHT 2015,2017 -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2018 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
@@ -518,6 +518,10 @@ attribute tank
<virtual/>
</entry>
<entry>
+ <name>ATTR_CHIP_EC_FEATURE_HW423589_OPTION1</name>
+ <virtual/>
+ </entry>
+ <entry>
<name>ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE</name>
<virtual/>
</entry>
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