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authorRaja Das <rajadas2@in.ibm.com>2016-09-08 03:49:46 -0500
committerAMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>2016-09-30 06:36:43 -0400
commite34f7c585774440c9e02879993c59bcf08723a9b (patch)
treebfca5b61468de3fe824f77cb1d5a457a02675f15 /src/test
parentd203132a331691e653aee54b339453b391b5e7a0 (diff)
downloadtalos-sbe-e34f7c585774440c9e02879993c59bcf08723a9b.tar.gz
talos-sbe-e34f7c585774440c9e02879993c59bcf08723a9b.zip
SBE Quiesce Implementation for FIFO/PSU
Change-Id: I25807d8114ed359347e842e2ca15d64f912865fb RTC: 149642 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test')
-rwxr-xr-xsrc/test/testcases/test.xml1
-rwxr-xr-xsrc/test/testcases/testGetCapabilities.py2
-rwxr-xr-xsrc/test/testcases/testQuiesce.py57
-rw-r--r--src/test/testcases/testQuiesce.xml45
4 files changed, 104 insertions, 1 deletions
diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml
index 32be24f4..668aa841 100755
--- a/src/test/testcases/test.xml
+++ b/src/test/testcases/test.xml
@@ -41,6 +41,7 @@
<include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include>
+ <include>../simics/targets/p9_nimbus/sbeTest/testQuiesce.xml</include>
<testcase>
<simcmd>sbe-trace 0</simcmd>
</testcase>
diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py
index 006d17c2..33971638 100755
--- a/src/test/testcases/testGetCapabilities.py
+++ b/src/test/testcases/testGetCapabilities.py
@@ -48,7 +48,7 @@ EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc
0xa7,0x0,0x0,0x1, # control Instruction
0x00,0x0,0x0,0x0];
-EXPDATA3 = [0xa8,0x0,0x0,0x03, #getcapability/getSbeFFDC
+EXPDATA3 = [0xa8,0x0,0x0,0x13, #getcapability/getSbeFFDC/quiesce
0x0,0x0,0x0,0x0,
0xc0,0xde,0xa8,0x02,
0x0,0x0,0x0,0x0,
diff --git a/src/test/testcases/testQuiesce.py b/src/test/testcases/testQuiesce.py
new file mode 100755
index 00000000..55aa2194
--- /dev/null
+++ b/src/test/testcases/testQuiesce.py
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testQuiesce.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+
+TESTDATA = [0,0,0,2,
+ 0,0,0xA8,0x06 ]
+
+EXPDATA = [0xc0,0xde,0xa8,0x06,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x3];
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+ testUtil.writeUsFifo( TESTDATA )
+ testUtil.writeEot( )
+ testUtil.readDsFifo( EXPDATA )
+ testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml
new file mode 100644
index 00000000..8b502949
--- /dev/null
+++ b/src/test/testcases/testQuiesce.xml
@@ -0,0 +1,45 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/test/testcases/testQuiesce.xml $ -->
+<!-- -->
+<!-- OpenPOWER sbe Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2016 -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<?xml version="1.0" encoding="UTF-8"?>
+
+ <!-- SBE Quiesce Test case -->
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testQuiesce.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+ <!-- A Get Capabilities chip-op should succeed post the Quiesce -->
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+ <!-- A GetScom/PutScom chip-op should succeed post the Quiesce -->
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+ <!-- An Adu put chip-op should succeed post the Quiesce -->
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
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