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authorspashabk-in <shakeebbk@in.ibm.com>2016-11-22 04:29:40 -0600
committerSachin Gupta <sgupta2m@in.ibm.com>2017-01-19 01:07:30 -0500
commit58ca2d13fcdde12e57950fbd1254070a7f107fd7 (patch)
treee7db260f807d8daacf740ddde5306316ba47ddd7 /src/test
parent38a51f1b67f180817adb61ab47aea49bf75143c7 (diff)
downloadtalos-sbe-58ca2d13fcdde12e57950fbd1254070a7f107fd7.tar.gz
talos-sbe-58ca2d13fcdde12e57950fbd1254070a7f107fd7.zip
SBE fastarray chip-op
RTC:120758 Change-Id: I00256ab35e3ad07c72ee6c5cb7b5d1c24f4fac55 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32939 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test')
-rwxr-xr-xsrc/test/testcases/test.xml1
-rw-r--r--src/test/testcases/testFastAccess.xml28
-rw-r--r--src/test/testcases/testFastArray.py80
3 files changed, 109 insertions, 0 deletions
diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml
index 76d1998e..53366256 100755
--- a/src/test/testcases/test.xml
+++ b/src/test/testcases/test.xml
@@ -43,6 +43,7 @@
<include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testSystemFabricMap.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testArrayAccess.xml</include>
+ <include>../simics/targets/p9_nimbus/sbeTest/testFastAccess.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testExecutorCntrlTimer.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testQuiesce.xml</include>
diff --git a/src/test/testcases/testFastAccess.xml b/src/test/testcases/testFastAccess.xml
new file mode 100644
index 00000000..00c8fe49
--- /dev/null
+++ b/src/test/testcases/testFastAccess.xml
@@ -0,0 +1,28 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: src/test/testcases/testFastAccess.xml $ -->
+<!-- -->
+<!-- OpenPOWER sbe Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+<!-- Control Trace Array Test case -->
+<testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testFastArray.py</simcmd>
+ <exitonerror>yes</exitonerror>
+</testcase>
diff --git a/src/test/testcases/testFastArray.py b/src/test/testcases/testFastArray.py
new file mode 100644
index 00000000..69c062e6
--- /dev/null
+++ b/src/test/testcases/testFastArray.py
@@ -0,0 +1,80 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testFastArray.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016,2017
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+
+CONTROL_FAST_ARRAY_SETUP_TESTDATA = [0, 0, 0, 0x05,
+ 0, 0, 0xA6, 0x01,
+ 0, 0x02, 0x20, 0x01, #PERV, 0x20 - Core chiplet, setup
+ 0x12, 0x34, 0x56, 0x78, #data[0-31]
+ 0x9a, 0xbc, 0xde, 0xf0] #data[32-63]
+CONTROL_FAST_ARRAY_CATCHUP_TESTDATA= [0, 0, 0, 0x05,
+ 0, 0, 0xA6, 0x01,
+ 0, 0x02, 0x20, 0x02, #PERV, 0x20 - Core chiplet, catchup
+ 0x00, 0x00, 0x00, 0x00, #data[0-31]
+ 0x00, 0x00, 0x00, 0x01] #data[32-63]
+CONTROL_FAST_ARRAY_CLEANUP_TESTDATA = [0, 0, 0, 0x05,
+ 0, 0, 0xA6, 0x01,
+ 0, 0x02, 0x20, 0x03, #PERV, 0x20 - Core chiplet, cleanup
+ 0x12, 0x34, 0x56, 0x78, #dont care
+ 0x9a, 0xbc, 0xde, 0xf0] #dont care
+
+CONTROL_FAST_ARRAY_VALID = [0xC0, 0xDE, 0xA6, 0x01,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0x03]
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+ print ("\nStarting control fastarray test")
+ print ("\nTest case: Setup")
+ testUtil.writeUsFifo( CONTROL_FAST_ARRAY_SETUP_TESTDATA)
+ testUtil.writeEot( )
+ testUtil.readDsFifo( CONTROL_FAST_ARRAY_VALID)
+ testUtil.readEot( )
+ print ("\nTest case: Catchup")
+ testUtil.writeUsFifo(CONTROL_FAST_ARRAY_CATCHUP_TESTDATA)
+ testUtil.writeEot( )
+ testUtil.readDsFifo( CONTROL_FAST_ARRAY_VALID)
+ testUtil.readEot( )
+ print ("\nTest case: Cleanup")
+ testUtil.writeUsFifo( CONTROL_FAST_ARRAY_CLEANUP_TESTDATA)
+ testUtil.writeEot( )
+ testUtil.readDsFifo( CONTROL_FAST_ARRAY_VALID)
+ testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
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