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author | spashabk-in <shakeebbk@in.ibm.com> | 2018-04-25 04:10:36 -0500 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-05-15 02:15:20 -0400 |
commit | e3dd8facc038086da5224f60d3bf3f57d82da8f6 (patch) | |
tree | 5b2072963af5901872b9061b281e74f5f8ef15d9 /src/test/testcases | |
parent | af40291dc92d9e67173b7d538cb580c4aa557fee (diff) | |
download | talos-sbe-e3dd8facc038086da5224f60d3bf3f57d82da8f6.tar.gz talos-sbe-e3dd8facc038086da5224f60d3bf3f57d82da8f6.zip |
Fence all chip-ops in QUIESCE state
Change-Id: I42ffb9db5503ad36636a989d54041220e159e6fc
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57793
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test/testcases')
-rw-r--r-- | src/test/testcases/testMemUtil.py | 9 | ||||
-rwxr-xr-x | src/test/testcases/testQuiesce.py | 7 | ||||
-rw-r--r-- | src/test/testcases/testQuiesce.xml | 25 |
3 files changed, 14 insertions, 27 deletions
diff --git a/src/test/testcases/testMemUtil.py b/src/test/testcases/testMemUtil.py index fce1eae2..ea987fef 100644 --- a/src/test/testcases/testMemUtil.py +++ b/src/test/testcases/testMemUtil.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2017 +# Contributors Listed Below - COPYRIGHT 2017,2018 # [+] International Business Machines Corp. # # @@ -149,7 +149,7 @@ def getmem(addr, len, flags): testUtil.readEot( ) return data[:lenExp] -def getmem_failure(addr, len, flags, responseWord): +def getmem_failure(addr, len, flags, responseWord, withLen = True): testUtil.runCycles( 10000000 ) req = (getsingleword(6) + [0, 0, 0xA4, 0x01] @@ -158,7 +158,10 @@ def getmem_failure(addr, len, flags, responseWord): + getsingleword(len)) testUtil.writeUsFifo(req) testUtil.writeEot( ) - expResp = ([0x0, 0x0, 0x0, 0x0] + lenWord = [] + if withLen: + lenWord = [0x0, 0x0, 0x0, 0x0] + expResp = (lenWord + [0xc0,0xde,0xa4,0x01] + getsingleword(responseWord) + [0x0,0x0,0x0,0x03]) diff --git a/src/test/testcases/testQuiesce.py b/src/test/testcases/testQuiesce.py index 55aa2194..c6e6c987 100755 --- a/src/test/testcases/testQuiesce.py +++ b/src/test/testcases/testQuiesce.py @@ -5,7 +5,8 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2015,2016 +# Contributors Listed Below - COPYRIGHT 2015,2018 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +25,7 @@ import sys sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil +import testMemUtil err = False TESTDATA = [0,0,0,2, @@ -43,6 +45,9 @@ def main( ): testUtil.readDsFifo( EXPDATA ) testUtil.readEot( ) + # fail get mem in quiesce state + testMemUtil.getmem_failure(0x08000000, 128*2, 0x02, 0x00010008, False) + #------------------------------------------------- # Calling all test code #------------------------------------------------- diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml index 9619b7ae..21794d9f 100644 --- a/src/test/testcases/testQuiesce.xml +++ b/src/test/testcases/testQuiesce.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -28,25 +28,4 @@ <testcase> <simcmd>run-python-file targets/p9_nimbus/sbeTest/testQuiesce.py</simcmd> <exitonerror>yes</exitonerror> - </testcase> - <!-- A Get Capabilities chip-op should succeed post the Quiesce --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <!-- A GetScom/PutScom chip-op should succeed post the Quiesce --> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - <!-- Taking out this test-case since this requires clock now, and we have - already done stop clock before quiesce. Somehow there is dependency - of clock with ADU, this used to work in DD1. - We can't move stopclock testcase below this since stop clock is from - seeprom region and quiesce prohibits seeprom access. - Disabling ADU access after quiesce operation. --> - <!-- An Adu put chip-op should succeed post the Quiesce --> - <!--<testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> --> + </testcase>
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