diff options
| author | Shakeeb <shakeebbk@in.ibm.com> | 2016-08-31 15:15:19 -0500 |
|---|---|---|
| committer | AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> | 2016-09-01 07:07:29 -0400 |
| commit | 1008ef70a71fcfdec398ff30923d5025991c85f4 (patch) | |
| tree | b22fc2a7cf2c8414ca20dfc7489a7f6d1a145878 /src/test/testcases | |
| parent | 28cb5c42ddba0cb9d2a86f43785c60499170ef2f (diff) | |
| download | talos-sbe-1008ef70a71fcfdec398ff30923d5025991c85f4.tar.gz talos-sbe-1008ef70a71fcfdec398ff30923d5025991c85f4.zip | |
SBE code restructure: cleanup
Change-Id: I354cc79ba25b843fdb1a7524a19b8d0c41bd9051
RTC:159709
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29060
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Diffstat (limited to 'src/test/testcases')
52 files changed, 4806 insertions, 0 deletions
diff --git a/src/test/testcases/ffdc.xml b/src/test/testcases/ffdc.xml new file mode 100755 index 00000000..b8773556 --- /dev/null +++ b/src/test/testcases/ffdc.xml @@ -0,0 +1,41 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/ffdc.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + <!--Collect FFDC --> + <test> + <subtest> + <testcase> + <simcmd>sbe-trace 0</simcmd> + </testcase> + <testcase> + <simcmd>p9Proc0.sbe.ppe->ppe_state</simcmd> + </testcase> + <testcase> + <simcmd>p9Proc0.proc_fifo->upstream_hw_fifo</simcmd> + </testcase> + <testcase> + <simcmd>p9Proc0.proc_fifo->downstream_hw_fifo</simcmd> + </testcase> + </subtest> + </test> diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml new file mode 100755 index 00000000..240ec318 --- /dev/null +++ b/src/test/testcases/test.xml @@ -0,0 +1,49 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/test.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> + +<integrationtest> + <platform startsimargs="--notar --norun --sim_parms -nre"> + <machine>%%machine%%</machine> + <test> + <testcase> + <simcmd>p9Proc0.pib_psu->tppsu_tpbr_interrupt_msg_available=[NIL]</simcmd> + </testcase> + <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include> + <!-- TODO via 158768: Enable pba test case--> + <!-- include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include --> + <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testCntlInstruction.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testRegAccess.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testFifoReset.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include> + <testcase> + <simcmd>sbe-trace 0</simcmd> + </testcase> + </test> + </platform> +</integrationtest> diff --git a/src/test/testcases/testAbort.py b/src/test/testcases/testAbort.py new file mode 100755 index 00000000..c8be29bf --- /dev/null +++ b/src/test/testcases/testAbort.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAbort.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA8,0x04 ] + +EXPDATA = [0xc0,0xde,0xa8,0x04, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testAduMem.xml b/src/test/testcases/testAduMem.xml new file mode 100644 index 00000000..fe3194d7 --- /dev/null +++ b/src/test/testcases/testAduMem.xml @@ -0,0 +1,42 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testAduMem.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_ecc.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_itag.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_withEccItag.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testAduMem_ecc.py b/src/test/testcases/testAduMem_ecc.py new file mode 100644 index 00000000..9741d1cb --- /dev/null +++ b/src/test/testcases/testAduMem_ecc.py @@ -0,0 +1,68 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAduMem_ecc.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +LOOP_COUNT = 1 + +GETMEMADU_TESTDATA_ECC = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0xAD, #CoreChipletId/EccByte/Flags - CacheInhibit/FastMode/NoTag/Ecc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x20] # length of data + +GETMEMADU_EXPDATA_ECC = [0x00,0x00,0x00,0x24, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetMemAdu with Ecc + testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC) + testUtil.writeEot( ) + + testUtil.readDsEntry ( 9 ) + testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testAduMem_itag.py b/src/test/testcases/testAduMem_itag.py new file mode 100644 index 00000000..33a594ab --- /dev/null +++ b/src/test/testcases/testAduMem_itag.py @@ -0,0 +1,66 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAduMem_itag.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +GETMEMADU_TESTDATA_ITAG = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0xB5, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/NoEcc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x40] # length of data + +GETMEMADU_EXPDATA_ITAG = [0x00,0x00,0x00,0x48, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetMemAdu with Itag + testUtil.writeUsFifo( GETMEMADU_TESTDATA_ITAG ) + testUtil.writeEot( ) + + testUtil.readDsEntry ( 18 ) + testUtil.readDsFifo( GETMEMADU_EXPDATA_ITAG ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testAduMem_noEccNoItag.py b/src/test/testcases/testAduMem_noEccNoItag.py new file mode 100644 index 00000000..354ad8bd --- /dev/null +++ b/src/test/testcases/testAduMem_noEccNoItag.py @@ -0,0 +1,99 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAduMem_noEccNoItag.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +LOOP_COUNT = 1 + +PUTMEMADU_CNTLDATA = [0,0,0,0, + 0,0,0xA4,0x02, + 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x10] # length of data + +PUTMEMADU_TESTDATA = [0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9] + +PUTMEMADU_EXPDATA = [0x00,0x00,0x00,0x10, # length of data + 0xc0,0xde,0xa4,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + + +GETMEMADU_TESTDATA = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x10] # length of data + +GETMEMADU_EXPDATA = [0xab,0xcd,0xef,0x12, #data + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9, + 0x00,0x00,0x00,0x10, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + #PutMemAdu Test + testUtil.writeUsFifo( PUTMEMADU_CNTLDATA ) + testUtil.writeUsFifo( PUTMEMADU_TESTDATA ) + testUtil.writeEot( ) + + testUtil.readDsFifo( PUTMEMADU_EXPDATA ) + testUtil.readEot( ) + + # GetMemAdu test + testUtil.writeUsFifo( GETMEMADU_TESTDATA ) + testUtil.writeEot( ) + + testUtil.readDsFifo( GETMEMADU_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testAduMem_withEccItag.py b/src/test/testcases/testAduMem_withEccItag.py new file mode 100644 index 00000000..d3c9f9c0 --- /dev/null +++ b/src/test/testcases/testAduMem_withEccItag.py @@ -0,0 +1,66 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAduMem_withEccItag.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +GETMEMADU_TESTDATA_ECC_ITAG = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0xBD, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/Ecc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x40] # length of data + +GETMEMADU_EXPDATA_ECC_ITAG = [0x00,0x00,0x00,0x50, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetMemAdu with Ecc with Itag test + testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC_ITAG ) + testUtil.writeEot( ) + + testUtil.readDsEntry ( 20 ) + testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC_ITAG ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testAduMem_withEccWithItagReadWrite.py b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py new file mode 100644 index 00000000..3d294915 --- /dev/null +++ b/src/test/testcases/testAduMem_withEccWithItagReadWrite.py @@ -0,0 +1,96 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testAduMem_withEccWithItagReadWrite.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +LOOP_COUNT = 1 + +PUTMEMADU_CNTLDATA = [0,0,0,0, + 0,0,0xA4,0x02, + 0,0x07,0x0,0xBD, #CoreChipletId/EccByteTrue/Flags -> EccOverride/CacheInhibit/FastMode/Tag/EccOverride/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x08] # length of data + +PUTMEMADU_TESTDATA = [0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21] + +PUTMEMADU_EXPDATA = [0x00,0x00,0x00,0x0a, # length of data + 0xc0,0xde,0xa4,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + + + +GETMEMADU_TESTDATA = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0xBD, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/Ecc/AutoIncr/Adu/Proc + 0,0,0,0, # Addr Upper 32 bit + 0x08,0x00,0x00,0x00, # Addr Lower 32 bit + 0x00,0x00,0x00,0x08] # length of data + +GETMEMADU_EXPDATA = [0xab,0xcd,0xef,0x12, #data + 0xba,0xdc,0xfe,0x21, + 0x01,0x07,0,0, #First Byte is iTag / Second Byte is ECC + 0x00,0x00,0x00,0x0a, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + #PutMemAdu Test + testUtil.writeUsFifo( PUTMEMADU_CNTLDATA ) + testUtil.writeUsFifo( PUTMEMADU_TESTDATA ) + testUtil.writeEot( ) + + testUtil.readDsFifo( PUTMEMADU_EXPDATA ) + testUtil.readEot( ) + + # GetMemAdu test + testUtil.writeUsFifo( GETMEMADU_TESTDATA ) + testUtil.writeEot( ) + + testUtil.readDsFifo( GETMEMADU_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testCntlInstruction.py b/src/test/testcases/testCntlInstruction.py new file mode 100644 index 00000000..f3143e70 --- /dev/null +++ b/src/test/testcases/testCntlInstruction.py @@ -0,0 +1,473 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testCntlInstruction.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + +#Invalid Input +INST_INVALID_TESTDATA = [0,0,0,3, + 0,0,0xa7,0x01, + 0,1,0x20,0xee] + + +INST_INVALID_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01, + 0x00,0x02,0x00,0x0A, + 0x00,0x00,0x00,0x03] + +# STOP Ins +# core 0 thread 0 STOP WARN FLAG as true +INST_STOP_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x01] + +# core 0 thread 1 STOP WARN FLAG as true +INST_STOP_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x11] + +# core 0 thread 2 STOP WARN FLAG as true +INST_STOP_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x21] + +# core 0 thread 3 STOP with WARN FLAG as true +INST_STOP_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x31] + +# core 0 thread 0 STOP WARN FLAG as false +INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x01] + +# core 0 thread 1 STOP WARN FLAG as false +INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x11] + +# core 0 thread 2 STOP WARN FLAG as false +INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x21] + +# core 0 thread 3 STOP WARN FLAG as false +INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x31] + +# Stop All thread in Core0 with warn flag true +INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf1] + +# Stop All thread in Core0 with warn flag false +INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0xf1] + + +# START Ins +# core 0 thread 0 START WARN FLAG as true +INST_START_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x00] + +# core 0 thread 1 START WARN FLAG as true +INST_START_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x10] + +# core 0 thread 2 START WARN FLAG as true +INST_START_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x20] + +# core 0 thread 3 START with WARN FLAG as true +INST_START_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x30] + +# core 0 thread 0 START WARN FLAG as false +INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x00] + +# core 0 thread 1 START WARN FLAG as false +INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x10] + +# core 0 thread 2 START WARN FLAG as false +INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x20] + +# core 0 thread 3 START WARN FLAG as false +INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x30] + +# Start All thread in Core0 with warn flag true +INST_START0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf0] + +# Start All thread in Core0 with warn flag false +INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0xf0] + +# STEP Ins +# core 0 thread 0 STEP WARN FLAG as true +INST_STEP_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x02] + +# core 0 thread 1 STEP WARN FLAG as true +INST_STEP_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x12] + +# core 0 thread 2 STEP WARN FLAG as true +INST_STEP_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x22] + +# core 0 thread 3 STEP with WARN FLAG as true +INST_STEP_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x32] + +# core 0 thread 0 STEP WARN FLAG as false +INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x02] + +# core 0 thread 1 STEP WARN FLAG as false +INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x12] + +# core 0 thread 2 STEP WARN FLAG as false +INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x22] + +# core 0 thread 3 STEP WARN FLAG as false +INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x32] + +# Step All thread in Core0 with warn flag true +INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf2] + +# Step All thread in Core0 with warn flag false +INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0xf2] + +# SRESET Ins +# core 0 thread 0 SRESET WARN FLAG as true +INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x03] + +# core 0 thread 1 SRESET WARN FLAG as true +INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x13] + +# core 0 thread 2 SRESET WARN FLAG as true +INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x23] + +# core 0 thread 3 SRESET with WARN FLAG as true +INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0x33] + +# core 0 thread 0 SRESET WARN FLAG as false +INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x03] + +# core 0 thread 1 SRESET WARN FLAG as false +INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x13] + +# core 0 thread 2 SRESET WARN FLAG as false +INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x23] + +# core 0 thread 3 SRESET WARN FLAG as false +INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0x33] + +# Sreset All thread in Core0 with warn flag true +INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf3] + +# Sreset All thread in Core0 with warn flag false +INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,0,0x20,0xf3] + + +INST_EXPDATA = [0xc0,0xde,0xa7,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +INST_EXPDATA_ERR = [0xc0,0xde,0xa7,0x01, + 0x00,0xFE,0x00,0x0A, + 0x00,0x00,0x00,0x03] + +STOP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, + 0x00,0xFE,0x00,0x0A, + 0xFF,0xDC,0x00,0x02, + 0x00,0xCE,0xBC,0xB2, + 0x00,0x00,0x00,0x05] + +START_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, + 0x00,0xFE,0x00,0x0A, + 0xFF,0xDC,0x00,0x02, + 0x00,0x25,0x64,0xDB, + 0x00,0x00,0x00,0x05] + +STEP_INST_EXPDATA_ERR_WTH_FFDC = [0xc0,0xde,0xa7,0x01, + 0x00,0xFE,0x00,0x0A, + 0xFF,0xDC,0x00,0x02, + 0x00,0x0D,0x06,0x8E, + 0x00,0x00,0x00,0x05] + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + #Try an invalid data case + testUtil.writeUsFifo( INST_INVALID_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_INVALID_EXPDATA_ERR ) + testUtil.readEot( ) + + # Control Instruction Message - Stop + testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_0_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_1_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_2_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP_0_3_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + #stop all thread in core0 + testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + # Control Instruction Message - Start + testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + + testUtil.writeUsFifo( INST_START_0_0_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_1_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_2_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START_0_3_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + #start all thread in core0 + testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( START_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + # Control Instruction Message - Step + testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_0_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_1_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_2_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP_0_3_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + #step all thread in core0 + testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_STEP0_ALL_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( STEP_INST_EXPDATA_ERR_WTH_FFDC ) + testUtil.readEot( ) + + # Control Instruction Message - Sreset + testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_0_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_1_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_2_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET_0_3_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + + #step all thread in core0 + testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( INST_SRESET0_ALL_TESTDATA_WITHOUT_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testCntlInstruction.xml b/src/test/testcases/testCntlInstruction.xml new file mode 100755 index 00000000..ef16cd40 --- /dev/null +++ b/src/test/testcases/testCntlInstruction.xml @@ -0,0 +1,30 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testCntlInstruction.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testCntlInstruction.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testContinueMpipl.py b/src/test/testcases/testContinueMpipl.py new file mode 100755 index 00000000..17f9f7fa --- /dev/null +++ b/src/test/testcases/testContinueMpipl.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testContinueMpipl.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA9,0x02 ] + +EXPDATA = [0xc0,0xde,0xa9,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testContinueSbeBoot.py b/src/test/testcases/testContinueSbeBoot.py new file mode 100755 index 00000000..f3542eda --- /dev/null +++ b/src/test/testcases/testContinueSbeBoot.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testContinueSbeBoot.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA1,0x02 ] + +EXPDATA = [0xc0,0xde,0xa1,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testEnterMpipl.py b/src/test/testcases/testEnterMpipl.py new file mode 100755 index 00000000..ce99c81b --- /dev/null +++ b/src/test/testcases/testEnterMpipl.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testEnterMpipl.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA9,0x01 ] + +EXPDATA = [0xc0,0xde,0xa9,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testExecutorMemory.py b/src/test/testcases/testExecutorMemory.py new file mode 100644 index 00000000..fe1b8526 --- /dev/null +++ b/src/test/testcases/testExecutorMemory.py @@ -0,0 +1,80 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testExecutorMemory.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +''' +############################################################# +# @file testExecutor.py +# @author: George Keishing <gkeishin@in.ibm.com> +# @brief Framework to test Host SBE interface on simics +# +# Created on March 29, 2016 +# ---------------------------------------------------- +# @version Developer Date Description +# ---------------------------------------------------- +# 1.0 gkeishin 29/03/16 Initial create +############################################################# +''' + +import testClass as testObj +import testRegistry as reg + +#------------------------------- +# This is a Test Expected Data +#------------------------------- +''' +This data are the values or strings that needs to be validated for the test. +''' +SBE_TEST_EXPECT_DEFAULT = "None" + +HOST_TEST_EXPECT_MAGIC = "00000000DEADBEEF" + +sbe_test_data = ( + #----------------------------------------------------------------------------------------------------- + # OP Reg Mem Length (bytes) size Test Expected Data Description + #----------------------------------------------------------------------------------------------------- + #["memRead", reg.MEM_ADDR, 0xA00000, 8, HOST_TEST_EXPECT_MAGIC, "Reading data from the address"], + ["memRead", reg.MEM_ADDR, 0x50, 8, HOST_TEST_EXPECT_MAGIC, "Reading data from the address"], + ) + +#------------------------- +# Main Function +#------------------------- +def main(): + + # Intialize the class obj instances + print "\n Initializing Registry instances ...." + regObj = testObj.registry() # Registry obj def for operation + + print "\n Execute SBE Test set [ Indirect Commands ] ...\n" + # Sim obj Target Test set + rc_test = regObj.ExecuteTestOp(testObj.simMemObj,sbe_test_data) + if rc_test != testObj.SUCCESS: + print " SBE Test data set .. [ FAILED ] .." + else: + print " SBE Test data set .. [ SUCCESS ] " + print "\n" + +if __name__=="__main__": + main() + diff --git a/src/test/testcases/testExecutorPSU.py b/src/test/testcases/testExecutorPSU.py new file mode 100644 index 00000000..0b5d83d1 --- /dev/null +++ b/src/test/testcases/testExecutorPSU.py @@ -0,0 +1,140 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testExecutorPSU.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +''' +############################################################# +# @file testExecutor.py +# @author: George Keishing <gkeishin@in.ibm.com> +# @brief Framework to test Host SBE interface on simics +# +# Created on March 29, 2016 +# ---------------------------------------------------- +# @version Developer Date Description +# ---------------------------------------------------- +# 1.0 gkeishin 29/03/16 Initial create +############################################################# +''' + +import testPSUUtil +import testRegistry as reg + +#------------------------------- +# This is a Test Expected Data +#------------------------------- +''' +This data are the values or strings that needs to be validated for the test. +''' +SBE_TEST_EXPECT_DEFAULT = "None" + +HOST_TEST_EXPECT_DEFAULT = "None" +HOST_TEST_EXPECT_MBOX04 = "0000000000F0D101" + +''' +The test data is designed to accomodate as many as new entries a test needs +and can also increase the field in it to add new action associated with it. +''' +#--------------------- +# SBE side test data +#--------------------- +''' +Every test data entry itself represent an action associated with it's data. +The data is validated as it executes. + +The Test Expected Data if "None" signifies that this test entry is not to be +validated else it would validated against the expected value in the field. +On success returns macro SUCCESS else FAILURE + +Refer Documentation for the data used here directly. +''' + +sbe_test_data = ( + #----------------------------------------------------------------------------------------------------- + # OP Reg Value size Test Expected Data Description + #----------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000030100F0D101", 8, SBE_TEST_EXPECT_DEFAULT, "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0000000000001000", 8, SBE_TEST_EXPECT_DEFAULT, "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, SBE_TEST_EXPECT_DEFAULT, "Update SBE Doorbell register to interrupt SBE"], + ) + +#--------------------- +# Host side test data +#--------------------- +''' +This Host data indicates that this will validate the SBE test set execution +if the overall test is a success or failure. + +It can have as many entries which are needed to be validated. +''' +host_test_data = ( + #---------------------------------------------------------------------------------------------------------------- + # OP Reg Value size Test Expected Data Description + #---------------------------------------------------------------------------------------------------------------- + ["read", reg.REG_MBOX4, "0000000000000000", 8, HOST_TEST_EXPECT_MBOX04, "Reading Host MBOX4 data to Validate"], + ) + +''' +User can define a function which does some task and returns SUCCESS or FAILURE. +one can simply call that function like any OP in the test data and still work. + +Define those function in testClassUtil.py context for this to work. +''' + +SAMPLE_TEST_EXPECT_FUNC = "None" +PARM_DATA = [1, 2, 3, 4] # sample 4 input paramters +sample_test_data = ( + #---------------------------------------------------------------------------------------------------------------- + # OP function Name Parameters NA Test Expected Data Description + #---------------------------------------------------------------------------------------------------------------- + ["func", "classUtilFuncSample", PARM_DATA, 0, SAMPLE_TEST_EXPECT_FUNC, "Load func and do task"], + ) + +#------------------------- +# Main Function +#------------------------- +def main(): + + # Intialize the class obj instances + print "\n Initializing Registry instances ...." + regObj = testPSUUtil.registry() # Registry obj def for operation + + print "\n Execute SBE Test set [ PSU ] ...\n" + # Sim obj Target Test set Raise Exception + rc_test = regObj.ExecuteTestOp(testPSUUtil.simSbeObj,sbe_test_data, True) + if rc_test != testPSUUtil.SUCCESS: + print " SBE Test data set .. [ Failed ] .." + else: + print " SBE Test data set .. [ OK ] " + print "\n Poll on Host side for INTR ...\n" + # Sim obj Target Test set Max timedout + rc_intr = regObj.pollingOn(testPSUUtil.simSbeObj,host_test_data,20) + if rc_intr == testPSUUtil.SUCCESS: + print " Interrupt Event Recieved .. Success !!" + else: + print " Interrupt not Recieved.. Exiting .." + + print "\n" + +if __name__=="__main__": + main() + diff --git a/src/test/testcases/testExecutorPutRing.py b/src/test/testcases/testExecutorPutRing.py new file mode 100644 index 00000000..59949a9f --- /dev/null +++ b/src/test/testcases/testExecutorPutRing.py @@ -0,0 +1,225 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testExecutorPutRing.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import testPSUUtil +import testRegistry as reg +import testUtil + +#------------------------------- +# This is a Test Expected Data +#------------------------------- +''' +This data are the values or strings that needs to be validated for the test. +''' +''' +#------------------------------------------------------------------------------------------------------------------------------ +# SBE side test data - Target - Pervasive(Core), Chiplet Id - 32, Ring ID - ec_func(224), mode - 0x0020(RING_MODE_HEADER_CHECK) +#------------------------------------------------------------------------------------------------------------------------------ +''' +sbe_test_data1 = ( + #----------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #----------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0002002000E00020", 8, "None", "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], + ) +''' +#------------------------------------------------------------------------------------------------------------------------------ +# SBE side test data - Target - Pervasive(Perv), Chiplet Id - 1, Ring ID - perv_fure(00), mode - 0x0020(RING_MODE_HEADER_CHECK) +#------------------------------------------------------------------------------------------------------------------------------ +''' +sbe_test_data2 = ( + #-------------------------------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #-------------------------------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0002000100000020", 8, "None", "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], + ) +''' +#--------------------- +# SBE side test data - Target - PROC CHIP, Chiplet Id - x, Ring ID - ob0_fure(118), mode - 0x0020(RING_MODE_HEADER_CHECK) +#--------------------- +''' +sbe_test_data3 = ( + #-------------------------------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #-------------------------------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0000000600760020", 8, "None", "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], + ) +''' +#------------------------------------------------------------------------------------------------------------------------------ +# SBE side test data - Target - EX, Chiplet Id - 32, Ring ID - ex_l3_fure(176), mode - 0x0020(RING_MODE_HEADER_CHECK) +#------------------------------------------------------------------------------------------------------------------------------ +''' +sbe_test_data4 = ( + #----------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #----------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0001002000B00020", 8, "None", "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], + ) +''' +#------------------------------------------------------------------------------------------------------------------------------ +# SBE side test data - Target - Invalid target 0x10, Chiplet Id - 32, Ring ID - ex_l3_refr_repr(248), mode - 0x0020(RING_MODE_HEADER_CHECK) +#------------------------------------------------------------------------------------------------------------------------------ +''' +sbe_test_data5 = ( + #----------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #----------------------------------------------------------------------------------------------------- + ["write", reg.REG_MBOX0, "0000010000F0D301", 8, "None", "Writing to MBOX0 address"], + ["write", reg.REG_MBOX1, "0010002000F80020", 8, "None", "Writing to MBOX1 address"], + ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"], + ) +''' +#--------------------- +# Host side test data - SUCCESS +#--------------------- +''' +host_test_data_success = ( + #---------------------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #---------------------------------------------------------------------------------------------------------------- + ["read", reg.REG_MBOX4, "0", 8, "0000000000F0D301", "Reading Host MBOX4 data to Validate"], + ) +''' +#--------------------- +# Host side test data - FAILURE +#--------------------- +''' +host_test_data_failure5 = ( + #---------------------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #---------------------------------------------------------------------------------------------------------------- + ["read", reg.REG_MBOX4, "0", 8, "0002000400F0D301", "Reading Host MBOX4 data to Validate"], + ) + +''' +#----------------------------------------------------------------------- +# Do not modify - Used to simulate interrupt on Ringing Doorbell on Host +#----------------------------------------------------------------------- +''' +host_polling_data = ( + #---------------------------------------------------------------------------------------------------------------- + # OP Reg ValueToWrite size Test Expected Data Description + #---------------------------------------------------------------------------------------------------------------- + ["read", reg.PSU_HOST_DOORBELL_REG_WO_OR, "0", 8, "8000000000000000", "Reading Host Doorbell for Interrupt"], + ) + +#------------------------- +# Main Function +#------------------------- +def main(): + # Run Simics initially + testUtil.runCycles( 10000000 ); + + # Intialize the class obj instances + regObj = testPSUUtil.registry() # Registry obj def for operation + + print "\n Execute SBE Test set1 [ Put Ring ] ...\n" + + ''' + Test Case 1 + ''' + # HOST->SBE data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data1 ) + + print "\n Poll on Host side for INTR ...\n" + #Poll on HOST DoorBell Register for interrupt + regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) + + #SBE->HOST data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) + + print "\n Execute SBE Test set2 [ Put Ring ] ...\n" + ''' + Test Case 2 + ''' + # HOST->SBE data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data2 ) + + print "\n Poll on Host side for INTR ...\n" + #Poll on HOST DoorBell Register for interrupt + regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) + + #SBE->HOST data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) + + print "\n Execute SBE Test set3 [ Put Ring ] ...\n" + ''' + Test Case 3 + ''' + # HOST->SBE data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data3 ) + + print "\n Poll on Host side for INTR ...\n" + #Poll on HOST DoorBell Register for interrupt + regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) + + #SBE->HOST data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) + + print "\n Execute SBE Test set4 [ Put Ring ] ...\n" + ''' + Test Case 4 + ''' + # HOST->SBE data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data4 ) + + print "\n Poll on Host side for INTR ...\n" + #Poll on HOST DoorBell Register for interrupt + regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) + + #SBE->HOST data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_success ) + + print "\n Execute SBE Test set5 [ Put Ring ] ...\n" + ''' + Test Case 5 + ''' + # HOST->SBE data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, sbe_test_data5 ) + + print "\n Poll on Host side for INTR ...\n" + #Poll on HOST DoorBell Register for interrupt + regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5 ) + + #SBE->HOST data set execution + regObj.ExecuteTestOp( testPSUUtil.simSbeObj, host_test_data_failure5 ) + +if __name__ == "__main__": + main() + if err: + print ( "\nTest Suite completed with error(s)" ) + #sys.exit(1) + else: + print ( "\nTest Suite completed with no errors" ) + #sys.exit(0); + + diff --git a/src/test/testcases/testExecutorPutRing.xml b/src/test/testcases/testExecutorPutRing.xml new file mode 100755 index 00000000..833484a8 --- /dev/null +++ b/src/test/testcases/testExecutorPutRing.xml @@ -0,0 +1,30 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testExecutorPutRing.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testExecutorPutRing.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testFifoReset.py b/src/test/testcases/testFifoReset.py new file mode 100644 index 00000000..41eb6563 --- /dev/null +++ b/src/test/testcases/testFifoReset.py @@ -0,0 +1,80 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testFifoReset.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest") +import testUtil + +err = False + +# Test data that only contains the command header +TESTDATA = [0, 0, 0, 3, + 0, 0, 0xA1, 0x01] + +# Complete test data +TESTDATA_FULL = [0, 0, 0, 3, + 0, 0, 0xA1, 0x01, + 0, 0x02, 0x00, 0x01] + +# Get capabilities command. This will ensure the DS FIFO gets full +TESTDATA_2 = [0, 0, 0, 2, + 0, 0, 0xA8, 0x02] + +def main(): + try: + testUtil.runCycles(10000000) + # Send a partial chip-op + testUtil.writeUsFifo(TESTDATA) + testUtil.resetFifo() + # Make sure both the upstream and downstrem FIFOs are clear after the reset + testUtil.waitTillUsFifoEmpty() + testUtil.waitTillDsFifoEmpty() + # Now send a complete chip-op on the upstream FIFO + testUtil.writeUsFifo(TESTDATA_FULL) + testUtil.writeEot() + testUtil.resetFifo() + # Make sure both the upstream and downstrem FIFOs are clear after the reset + testUtil.waitTillUsFifoEmpty() + testUtil.waitTillDsFifoEmpty() + # Now send a get capabilities chip-op, so that in response, the DS FIFO + # gets full before we do a reset + testUtil.writeUsFifo(TESTDATA_2) + testUtil.writeEot() + testUtil.resetFifo() + # Make sure both the upstream and downstrem FIFOs are clear after the reset + testUtil.waitTillUsFifoEmpty() + testUtil.waitTillDsFifoEmpty() + except: + print("\nTest completed with error(s), Raise error") + raise + print("\nTest completed with no errors") + +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testFifoReset.xml b/src/test/testcases/testFifoReset.xml new file mode 100644 index 00000000..b9ef674d --- /dev/null +++ b/src/test/testcases/testFifoReset.xml @@ -0,0 +1,35 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testFifoReset.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <!-- SBE FIFO reset Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testFifoReset.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- An istep chip-op should succeed post the FIFO reset --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalidFenced.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> diff --git a/src/test/testcases/testGeneric.xml b/src/test/testcases/testGeneric.xml new file mode 100755 index 00000000..85ce990a --- /dev/null +++ b/src/test/testcases/testGeneric.xml @@ -0,0 +1,30 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testGeneric.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <!-- SBE Get Capabilities Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py new file mode 100755 index 00000000..4a61d761 --- /dev/null +++ b/src/test/testcases/testGetCapabilities.py @@ -0,0 +1,82 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testGetCapabilities.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA8,0x02 ] + +EXPDATA1 = [0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0, + 0xa1,0x0,0x0,0x01, # istep + 0x0,0x0,0x0,0x0, + 0xa2,0x0,0x0,0x0f, #getscom/putscom/modifyscom/putscomundermask + 0x0,0x0,0x0,0x0, + 0xa3,0x0,0x0,0x1, #getring + 0x00,0x0,0x0,0x0]; + +EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc + 0x0,0x0,0x0,0x0, + 0xa5,0x0,0x0,0x03, #GetReg/PutReg + 0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0, + 0xa7,0x0,0x0,0x1, # control Instruction + 0x00,0x0,0x0,0x0]; + +EXPDATA3 = [0xa8,0x0,0x0,0x02, #getcapability + 0x0,0x0,0x0,0x0, + 0xc0,0xde,0xa8,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + # Ignore first two enteries ( major number, minor number + # and fw version) as they will keep on changing + testUtil.readDsEntry( 2 ) + testUtil.readDsFifo( EXPDATA1 ) + testUtil.readDsFifo( EXPDATA2 ) + testUtil.readDsFifo( EXPDATA3 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testGetMem.py b/src/test/testcases/testGetMem.py new file mode 100644 index 00000000..baf3b353 --- /dev/null +++ b/src/test/testcases/testGetMem.py @@ -0,0 +1,74 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testGetMem.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + +GETMEM_TESTDATA = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0x02, + 0,0,0,0, + 0x08,0x00,0x00,0x00, + 0x00,0x00,0x00,0x80] # length of data + +GETMEM_EXPDATA = [0x00,0x00,0x00,0x80, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetMem test + testUtil.writeUsFifo( GETMEM_TESTDATA ) + testUtil.writeEot( ) + # GetMem chipOp would send the read data first, + # thus, would attempt to read the expected length of data first + loop = 1 + while ( loop <= LOOP_COUNT ): + testUtil.readDsEntry ( 32 ) ## 32 entries ~ 128B PBA granule + loop += 1 + testUtil.readDsFifo( GETMEM_EXPDATA ) + testUtil.readEot( ) + + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testGetMem_expdata.py b/src/test/testcases/testGetMem_expdata.py new file mode 100644 index 00000000..df0b51f6 --- /dev/null +++ b/src/test/testcases/testGetMem_expdata.py @@ -0,0 +1,83 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testGetMem_expdata.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 4 + +GETMEM_TESTDATA = [0,0,0,0x6, + 0,0,0xA4,0x01, + 0,0,0x0,0x02, + 0,0,0,0, + 0x08,0x00,0x00,0x00, + 0x00,0x00,0x00,0x80] # length of data + +GETMEM_EXP_RESPHDR = [0x00,0x00,0x00,0x80, # length of data + 0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +GETMEM_EXP_RESPDATA = [0xAB,0xCD,0xEF,0x01, + 0xAB,0xCD,0xEF,0x02, + 0xAB,0xCD,0xEF,0x03, + 0xAB,0xCD,0xEF,0x04, + 0xAB,0xCD,0xEF,0x05, + 0xAB,0xCD,0xEF,0x06, + 0xAB,0xCD,0xEF,0x07, + 0xAB,0xCD,0xEF,0x08] + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetMem test + testUtil.writeUsFifo( GETMEM_TESTDATA ) + testUtil.writeEot( ) + # GetMem chipOp would send the read data first, + # thus, would attempt to read the expected length of data first + loop = 1 + while ( loop <= LOOP_COUNT ): + testUtil.readDsFifo ( GETMEM_EXP_RESPDATA ) + loop += 1 + testUtil.readDsFifo( GETMEM_EXP_RESPHDR ) + testUtil.readEot( ) + + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testGetRing.py b/src/test/testcases/testGetRing.py new file mode 100644 index 00000000..61fba66e --- /dev/null +++ b/src/test/testcases/testGetRing.py @@ -0,0 +1,95 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testGetRing.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + +#aligned Data +GETRING_TESTDATA = [0,0,0,0x6, + 0,0,0xA3,0x01, + 0xa,0xa,0xa,0xa, # address + 0,0,0,0x40, # length of data + 0x00,0x00,0x00,0x01] + +GETRING_EXPDATA = [0,0,0,0, #data + 0,0,0,0, #data + 0,0,0,0x40, # length of data + 0xc0,0xde,0xa3,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +#Un-aligned Data +GETRING_TESTDATA1 = [0,0,0,0x6, + 0,0,0xA3,0x01, + 0xa,0xa,0xa,0xa, # address + 0,0,0,0x45, # length of data + 0x00,0x00,0x00,0x01] + +GETRING_EXPDATA1 = [0,0,0,0, #data + 0,0,0,0, #data + 0,0,0,0, #data + 0,0,0,0, #data + 0,0,0,0x45, # length of data + 0xc0,0xde,0xa3,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # GetRing test - Aligned Data + testUtil.writeUsFifo( GETRING_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETRING_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + + # GetRing test - un-aligned Data + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( GETRING_TESTDATA1 ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETRING_EXPDATA1 ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testGetRing.xml b/src/test/testcases/testGetRing.xml new file mode 100755 index 00000000..808b2012 --- /dev/null +++ b/src/test/testcases/testGetRing.xml @@ -0,0 +1,29 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testGetRing.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetRing.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testIstep.xml b/src/test/testcases/testIstep.xml new file mode 100644 index 00000000..70cf2a62 --- /dev/null +++ b/src/test/testcases/testIstep.xml @@ -0,0 +1,332 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testIstep.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <!-- Invalid Istep Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalid.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- Positive Istep Test case --> + <testcase> + <simcmd>sbe-istep 2 2</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 3</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 4</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 5</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 6</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 7</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 8</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 9</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 10</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 11</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 12</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 13</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 14</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 15</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 16</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 2 17</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 1</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 2</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 3</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 4</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 5</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 6</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 7</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 8</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 9</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 10</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 11</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 12</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 13</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 14</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 15</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 16</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 17</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 18</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 19</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 20</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 21</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 3 22</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 1</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 2</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 3</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 4</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 5</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 6</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 7</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 8</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 9</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 10</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 11</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 12</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 13</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 14</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 15</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 16</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 17</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 18</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 19</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 20</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 21</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 22</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 23</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 24</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 25</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 26</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 27</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 28</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 29</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 30</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 31</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 32</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 33</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 4 34</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 5 1</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>sbe-istep 5 2</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- Invalid Istep Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalidFenced.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> diff --git a/src/test/testcases/testIstepAuto.py b/src/test/testcases/testIstepAuto.py new file mode 100755 index 00000000..bb1fcb5f --- /dev/null +++ b/src/test/testcases/testIstepAuto.py @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testIstepAuto.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +from sim_commands import * +import imp +err = False +testUtil = imp.load_source("testUtil", os.environ['SBE_TOOLS_PATH'] + "/testUtil.py") +EXPDATA = [0xc0,0xde,0xa1,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; +# MAIN Test Run Starts Here... +#------------------------------------------------- +def sbe_istep_func( major, minor ): + try: + TESTDATA = [0,0,0,3, + 0,0,0xA1,0x01, + 0,major,0,minor ] + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + except: + print ("\nTest completed with error(s). Raise error") + # TODO via RTC 142706 + # Currently simics commands created using hooks always return + # success. Need to check from simics command a way to return + # Calling non existant command to return failure + run_command("Command Failed"); + raise + print ("\nTest completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testIstepInvalid.py b/src/test/testcases/testIstepInvalid.py new file mode 100755 index 00000000..cd26b209 --- /dev/null +++ b/src/test/testcases/testIstepInvalid.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testIstepInvalid.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +TESTDATA = [0,0,0,3, + 0,0,0xA1,0x01, + 0,0x02,0x00,0x1] + +EXPDATA = [0xc0,0xde,0xa1,0x01, + 0x00,0x02,0x00,0x0A, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testIstepInvalidFenced.py b/src/test/testcases/testIstepInvalidFenced.py new file mode 100755 index 00000000..f64074b8 --- /dev/null +++ b/src/test/testcases/testIstepInvalidFenced.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testIstepInvalidFenced.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +TESTDATA = [0,0,0,3, + 0,0,0xA1,0x01, + 0,0x02,0x00,0x1] + +EXPDATA = [0xc0,0xde,0xa1,0x01, + 0x00,0x00,0x00,0x08, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testIstepSuccess.py b/src/test/testcases/testIstepSuccess.py new file mode 100755 index 00000000..f9e18436 --- /dev/null +++ b/src/test/testcases/testIstepSuccess.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testIstepSuccess.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +TESTDATA = [0,0,0,3, + 0,0,0xA1,0x01, + 0,0x02,0x00,0x2] + +EXPDATA = [0xc0,0xde,0xa1,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testModifyScom.py b/src/test/testcases/testModifyScom.py new file mode 100755 index 00000000..36d75aca --- /dev/null +++ b/src/test/testcases/testModifyScom.py @@ -0,0 +1,97 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testModifyScom.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + + +PUTSCOM_TESTDATA = [0,0,0,6, + 0,0,0xA2,0x02, + 0,0,0x0,0x00, + 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) + 0x00,0xff,0x00,0xff, + 0x00,0x00,0x00,0x00 ] + +PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +MODIFYSCOM_TESTDATA = [0,0,0,7, + 0,0,0xA2,0x03, + 0,0,0x0,0x01, + 0,0,0x0,0x00, + 0,0x05,0x00,0x3E, + 0xde,0x00,0xff,0x00, + 0x00,0x00,0x00,0x00] + +MODIFYSCOM_EXPDATA = [0xc0,0xde,0xa2,0x03, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETSCOM4MODIFYSCOM_TESTDATA = [0,0,0,4, + 0,0,0xA2,0x01, + 0,0,0x0,0x00, + 0,0x05,0x0,0x3E] + +GETSCOM4MODIFYSCOM_EXPDATA = [0xde,0xff,0xff,0xff, + 0x00,0x00,0x00,0x00, + 0xc0,0xde,0xa2,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + testUtil.writeUsFifo( PUTSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOM_EXPDATA ) + testUtil.readEot( ) + + testUtil.writeUsFifo( MODIFYSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( MODIFYSCOM_EXPDATA ) + testUtil.readEot( ) + + testUtil.writeUsFifo( GETSCOM4MODIFYSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETSCOM4MODIFYSCOM_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPSUUserUtil.py b/src/test/testcases/testPSUUserUtil.py new file mode 100644 index 00000000..383cb97c --- /dev/null +++ b/src/test/testcases/testPSUUserUtil.py @@ -0,0 +1,58 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPSUUserUtil.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +''' +############################################################# +# @file testClassUtil.py +# @author: George Keishing <gkeishin@in.ibm.com> +# @brief Framework utility fucntions for Host SBE +# interface on simics +# +# Created on March 29, 2016 +# ---------------------------------------------------- +# @version Developer Date Description +# ---------------------------------------------------- +# 1.0 gkeishin 29/03/16 Initial create +############################################################# +''' + +import testPSUUtil + +''' +Add your personalize functions here for execution but ensure it returns +either SUCCESS or FAILURE as an end result for generalization purpose. +''' + +########################################################################## +# Function : classUtilFuncSample +# +# @param i_paramArray : user supplied input array parameters +# +# @brief Function to do a task and returns SUCCCES or FAILURE +# +########################################################################## +def classUtilFuncSample(i_paramArray): + for input in i_paramArray: + print " classUtilFuncSample : parm: ",input + return testPSUUtil.SUCCESS diff --git a/src/test/testcases/testPSUUtil.py b/src/test/testcases/testPSUUtil.py new file mode 100644 index 00000000..efc7d5be --- /dev/null +++ b/src/test/testcases/testPSUUtil.py @@ -0,0 +1,376 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPSUUtil.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +''' +############################################################# +# @file testClass.py +# @author: George Keishing <gkeishin@in.ibm.com> +# @brief Framework class Host SBE interface on simics +# +# Created on March 29, 2016 +# ---------------------------------------------------- +# @version Developer Date Description +# ---------------------------------------------------- +# 1.0 gkeishin 29/03/16 Initial create +############################################################# +''' + +#------------------------- +# Imports packages +#------------------------- +import time +import conf +import testUtil +import testPSUUserUtil +from sim_commands import * + +#------------------------- +# Macros constants +#------------------------- +SUCCESS = 1 +FAILURE = 0 + +#------------------------- +# SIM OBJs +#------------------------- +''' +This is a simulator obj mapped. Refer simics folks if new objects are needed. +''' +simSbeObj = conf.p9Proc0.sbe.mibo_space +simHostObj = conf.p9Proc0.p9_mem_map.host_xscom_device_mm +simMemObj = conf.system_cmp0.phys_mem + +''' +This is a base MBOX registry address from 0..7 +''' +# Register MBOX 0..3 SBE side address in order +REGDATA_SBE = [ + 0x00680500, + 0x00680510, + 0x00680520, + 0x00680530 + ] + +# Register MBOX 4..7 host side address in order +REGDATA_HOST = [ + 0x00680540, + 0x00680550, + 0x00680560, + 0x00680570 + ] + +# Supporting Class objects +''' +Base function members definitions for set,get,read, write and others needed. +Keep it simple and modular so that it can be extended as a base class. +''' +#------------------ +# Registry class +#------------------ +class registry(object): + #------------------------------ + # Set the reg data + #------------------------------ + def setRegData(self, addr, value, size): + self.regAddr = addr + self.regVal = value + self.regSize = size + + #------------------------------ + # Read Reg value set or updated + #------------------------------ + def getRegData(self): + print " Addr : ",hex(self.regAddr) + print " Value : ",self.regVal + print " Size : ",self.regSize + + #------------------------------ + # Write to a Registry + #------------------------------ + def writeToReg(self, objType): + address = self.regAddr + value = self.stringToByte(self.regVal) + size = self.regSize + print " WData : 0x%s -> Byte Data %s"% (self.regVal,value) + print " Addr :", hex(address) + print " Size : %s Bytes"% size + + self.__write(objType,address,value,size) + return + + #------------------------------ + # Write to Registry 0..3 using + # test data directly. + #------------------------------ + def writeTestData(self, data): + simObj = SIM_get_interface(simSbeObj, "memory_space") + entryCount = len(data) + size = 8 + for i in range (entryCount): + value = stringToByte(data[i]) + print "\n Writting ", hex(REGDATA_SBE[i]) + print " %x %x %x %x %x %x %x %x" % (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]) + simObj.write(None, REGDATA_SBE[regIndex], + (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]), + size) + return + + #------------------------------ + # Write using SIM object + # 4/8 Bytes data + #------------------------------ + def __write(self, Targetobj, address, value, size): + simObj = SIM_get_interface(Targetobj, "memory_space") + if int(size) == 4: + simObj.write(None, address, + (value[0],value[1],value[2],value[3]), + size) + elif int(size) == 8: + simObj.write(None, address, + (value[0],value[1],value[2],value[3],value[4],value[5],value[6],value[7]), + size) + print " SIM obj: Write %s bytes [ OK ] " % size + return + + #--------------------------- + # Read from a Registry + #--------------------------- + def readFromReg(self, objType): + address = self.regAddr + size = self.regSize + value = self.regVal + if int(value) !=0: + print " RData :", value + print " Addr :", hex(address) + print " Size : %s Bytes"% size + + value = self.__read(objType,address,size) + return value + + #--------------------------- + # Read from a memomry + # Max Sim interface can read 8 + # byte data at a given time + #--------------------------- + def readFromMemory(self, objType, magicNum): + # Start addr + 8 bytes + address = self.regAddr + size = self.regSize # Max it can read is 8 Bytes + value = self.regVal # Max lentgth it should read + + MaxAddr = address + value # This is the addres range it could read + print " MaxAddr Range:",hex(MaxAddr) + OffsetAddr = address + print " OffsetAddr:",hex(OffsetAddr) + + print " Memory Entries to be read : %d" % (value/8) + print " Match Magic Number : ", magicNum + + while ( OffsetAddr <= MaxAddr): + sim_data = self.__read(objType,OffsetAddr,size) + print " ", hex(OffsetAddr),self.joinListDataToHex(sim_data).upper() + OffsetAddr += 8 + + if self.validateTestMemOp(sim_data,magicNum) == True: + print " Test validated .. [ OK ]" + return SUCCESS + + return FAILURE # Failed validation + + #------------------------------ + # Read using SIM Object + #------------------------------ + def __read(self, Targetobj, address, size): + simObj = SIM_get_interface(Targetobj, "memory_space") + value = simObj.read(None, address, size, 0x0) + #print " SIM obj: Read %s bytes [ OK ] " % size + return value + + #-------------------------------- + # Prepare the byte data from the + # string and return the list set + #------------------------------- + def stringToByte(self,value): + ''' + The sim interface doesnt take the values as it is .. + it takes as byte arrays + Ex: "0000030100F0D101" + '\x00\x00\x03\x01\x00\xf0\xd1\x01' + [0, 0, 3, 1, 0, 240, 209, 1] + ''' + # Convert it to a hex string + hex_val= value.decode("hex") + # Prepare the conversion to a list of byte values + value=map(ord, hex_val) + return value + + #--------------------------------------- + # Joing the list set data to hex data + # Reverse of the stringToByte logic + #--------------------------------------- + def joinListDataToHex(self, data): + # simics> (0, 0, 3, 1, 0, 240, 209, 1) + # Join this data into hex string 0xf0d101 + bit_shift=56 + hex_val = 0x0 + for val in data: + hex_val |= int(val) << bit_shift + bit_shift -=8 + return hex(hex_val) + + #---------------------------------------------------- + # Execute the read or write operation in loop as per + # Test data set pre-defined + #---------------------------------------------------- + def ExecuteTestOp(self, testOp, test_bucket, raiseException=True): + ''' + 3 prong steps : set data, read/write data, validate + ''' + #-------------------------------------------- + for l_params in test_bucket: + #-------------------------------------------- + print " Desc : %s " % l_params[5] + print " Op : %s " % l_params[0] + if "func" == l_params[0]: + print " Func : %s " % l_params[1] + if l_params[4] != "None": + print " Expect : %s " % l_params[4] + if "func" == l_params[0]: + print " Function Params :",l_params[2] + else: + # addr, value, size + self.setRegData(l_params[1],l_params[2],l_params[3]) + + # --------------------------------------------- + # Check the Op and perform the action + # read/write + # --------------------------------------------- + if "read" == l_params[0]: + sim_data = self.readFromReg(testOp) + print " ++++++++++++++++++++++++++++++++++++++++++" + print " simics Data : ", sim_data + print " simics Hex : ", self.joinListDataToHex(sim_data).upper() + + # Validate the test data + ''' + This field in the test entry holds the data + that needs validation against sim data. + ''' + if l_params[4] != "None": + if self.validateTestOp(sim_data,l_params[4]) == True: + print " Test validated .. [ OK ]" + else: + if(raiseException == True): + raise Exception('Data mistmach'); + return FAILURE # Failed validation + else: + print " ++++++++++++++++++++++++++++++++++++++++++" + elif "write" == l_params[0]: + self.writeToReg(testOp) + elif "memRead" == l_params[0]: + # (Sim obj) (Validate) + return self.readFromMemory(testOp, l_params[4]) + elif "func" == l_params[0]: + # Func name Params + rc = self.loadFunc( l_params[1], l_params[2] ) + return rc + else: + print "\n Invalid Test Data" + if(raiseException == True): + raise Exception('Invalid Test Data'); + return FAILURE # Unknown entry op + + print "\n" + return SUCCESS + + #---------------------------------------------------- + # Validate simulator data against test data + #---------------------------------------------------- + def validateTestOp(self, sim_data, test_data): + print " Test Expects : 0x%s " % test_data + print " Expect bytes : ", self.stringToByte(test_data) + if self.compareList(self.stringToByte(test_data), sim_data, "None") == True: + print " Test ... [ OK ] " + print " ++++++++++++++++++++++++++++++++++++++++++" + return SUCCESS + else: + print " Test Failed... !!!" + print " ++++++++++++++++++++++++++++++++++++++++++" + return FAILURE + + #---------------------------------------------------- + # Validate simulator data against test data + #---------------------------------------------------- + def validateTestMemOp(self, sim_data, test_data): + if self.compareList(self.stringToByte(test_data), sim_data,"memRead") == True: + return SUCCESS + return # Return nothing to check next memory entry + + + #---------------------------------------------------- + # Compare the result vs expected list data + # byte by byte + #---------------------------------------------------- + def compareList(self, expList, resList, opType): + for i in range(0,8): + if int(expList[i]) == int(resList[i]): + #print " %s : %s " % (expList[i],resList[i]) + continue + else: + if opType != "memRead": + print " Error \t %s : %s [ Mismatch ]" % (expList[i],resList[i]) + return False # mismatch + return # Return nothing for Next Mem byte read + return True + + #---------------------------------------------------- + # A basic loop poll mechanism + #---------------------------------------------------- + def pollingOn(self, simObj, test_data, retries=20): + for l_param in test_data: + while True: + print "\n***** Polling On result - retrials left [%d] " % retries + print "\n" + testUtil.runCycles( 1000000); + test_d = (l_param,) + rc = self.ExecuteTestOp(simObj, test_d, False) + if rc == SUCCESS: + print ('Polling Successful for - ' + l_param[5]) + break + elif retries <= 0: + print " Retrials exhausted... Exiting polling" + raise Exception('Polling Failed for - ' + l_param[5]); + break + else: + retries = retries - 1 + return FAILURE + + #---------------------------------------------------- + # Load the function and execute + #---------------------------------------------------- + def loadFunc(self, func_name, i_pArray ): + rc = testPSUUserUtil.__getattribute__(func_name)(i_pArray) + return rc # Either success or failure from func + + diff --git a/src/test/testcases/testPutGetInScom.py b/src/test/testcases/testPutGetInScom.py new file mode 100755 index 00000000..2e42a253 --- /dev/null +++ b/src/test/testcases/testPutGetInScom.py @@ -0,0 +1,82 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutGetInScom.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +# @TODO via RTC : 141905 +# Modify the test sequence in such a way that +# the test does not leave the Register value altered. + +# Indirect scom form 0 test case +PUTSCOM_TESTDATA = [0,0,0,6, + 0,0,0xA2,0x02, + 0x80,0x0,0x0,0x83, + 0x0D,0x01,0x0C,0x3F, + 0xde,0xca,0xff,0xee, + 0x00,0x00,0x12,0x34 ] + +PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETSCOM_TESTDATA = [0,0,0,4, + 0,0,0xA2,0x01, + 0x80,0x0,0x0,0x83, + 0x0D,0x01,0x0C,0x3F] + +GETSCOM_EXPDATA = [0x00,0x00,0x00,0x00, + 0x00,0x00,0x12,0x34, # Only last 16 bits will be returned + 0xc0,0xde,0xa2,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( PUTSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOM_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( GETSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETSCOM_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutGetMem.xml b/src/test/testcases/testPutGetMem.xml new file mode 100644 index 00000000..ae82868c --- /dev/null +++ b/src/test/testcases/testPutGetMem.xml @@ -0,0 +1,34 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testPutGetMem.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutMem.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetMem_expdata.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testPutGetRegFpr.py b/src/test/testcases/testPutGetRegFpr.py new file mode 100755 index 00000000..6bf0209e --- /dev/null +++ b/src/test/testcases/testPutGetRegFpr.py @@ -0,0 +1,81 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutGetRegFpr.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +PUTREG_TESTDATA = [0,0,0,9, + 0,0,0xA5,0x02, + 0x00,0x20,0x02,0x02, # two fpr registers + 0,0,0x0,0x01, + 0,0,0x0,0x0, + 0,0,0x0,0x1, + 0,0,0x0,0x02, + 0,0,0x0,0x0, + 0,0,0x0,0x2 ] + +PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETREG_TESTDATA = [0,0,0,5, + 0,0,0xA5,0x01, + 0x00,0x20,0x02,0x02, #two fpr registers + 0,0,0x0,0x01, + 0,0,0x0,0x02 ] + +GETREG_EXPDATA = [0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x02, + 0xc0,0xde,0xa5,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( PUTREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTREG_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( GETREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETREG_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutGetRegGpr.py b/src/test/testcases/testPutGetRegGpr.py new file mode 100755 index 00000000..871ff375 --- /dev/null +++ b/src/test/testcases/testPutGetRegGpr.py @@ -0,0 +1,81 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutGetRegGpr.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +PUTREG_TESTDATA = [0,0,0,9, + 0,0,0xA5,0x02, + 0x00,0x20,0x00,0x02, # two gpr registers + 0,0,0x0,0x07, + 0,0,0x0,0x0, + 0,0,0x0,0x1, + 0,0,0x0,0x08, + 0,0,0x0,0x0, + 0,0,0x0,0x2 ] + +PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETREG_TESTDATA = [0,0,0,5, + 0,0,0xA5,0x01, + 0x00,0x20,0x00,0x02, # two gpr registers + 0,0,0x0,0x07, + 0,0,0x0,0x08 ] + +GETREG_EXPDATA = [0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x02, + 0xc0,0xde,0xa5,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( PUTREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTREG_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( GETREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETREG_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutGetRegSpr.py b/src/test/testcases/testPutGetRegSpr.py new file mode 100755 index 00000000..d42e4c53 --- /dev/null +++ b/src/test/testcases/testPutGetRegSpr.py @@ -0,0 +1,81 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutGetRegSpr.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +PUTREG_TESTDATA = [0,0,0,9, + 0,0,0xA5,0x02, + 0x00,0x20,0x01,0x02, # two spr registers + 0,0,0x0,0x08, + 0,0,0x0,0x0, + 0,0,0x0,0x1, + 0,0,0x0,0x09, + 0,0,0x0,0x0, + 0,0,0x0,0x2 ] + +PUTREG_EXPDATA = [0xc0,0xde,0xa5,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETREG_TESTDATA = [0,0,0,5, + 0,0,0xA5,0x01, + 0x00,0x20,0x01,0x02, # two spr registers + 0,0,0x0,0x08, + 0,0,0x0,0x09 ] + +GETREG_EXPDATA = [0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x01, + 0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x02, + 0xc0,0xde,0xa5,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( PUTREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTREG_EXPDATA ) + testUtil.readEot( ) + testUtil.writeUsFifo( GETREG_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETREG_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutGetScom.py b/src/test/testcases/testPutGetScom.py new file mode 100755 index 00000000..9c8700e4 --- /dev/null +++ b/src/test/testcases/testPutGetScom.py @@ -0,0 +1,118 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutGetScom.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +# @TODO via RTC : 141905 +# Modify the test sequence in such a way that +# the test does not leave the Register value altered. + +PUTSCOM_TESTDATA = [0,0,0,6, + 0,0,0xA2,0x02, + 0,0,0x0,0x00, + 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) + 0xde,0xca,0xff,0xee, + 0x00,0x00,0x00,0x00 ] + +PUTSCOM_TESTDATA_INVALID = [0,0,0,6, + 0,0,0xA2,0x02, + 0,0,0x0,0x00, + # TODO via RTC 152952: This address is invalid for + # Nimbus but not for Cumulus + 0x0a,0x00,0x00,0x00, + 0xde,0xca,0xff,0xee, + 0x00,0x00,0x00,0x00 ] + +PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +PUTSCOM_EXPDATA_INVALID = [0xc0,0xde,0xa2,0x02, + 0x0,0xfe,0x0,0x11, + 0x00,0x0,0x0,0x04, + 0x00,0x0,0x0,0x04]; + +GETSCOM_TESTDATA = [0,0,0,4, + 0,0,0xA2,0x01, + 0,0,0x0,0x00, + 0,0x05,0x0,0x3E] + +GETSCOM_TESTDATA_INVALID = [0,0,0,4, + 0,0,0xA2,0x01, + 0,0,0x0,0x00, + # TODO via RTC: 152952: This address is invalid for + # Nimbus but not for Cumulus + 0x0a,0x0,0x0,0x0] + +GETSCOM_EXPDATA = [0xde,0xca,0xff,0xee, + 0x00,0x00,0x00,0x00, + 0xc0,0xde,0xa2,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETSCOM_EXPDATA_INVALID = [0xc0,0xde,0xa2,0x01, + 0x0,0xfe,0x0,0x11, + 0x00,0x0,0x0,0x04, + 0x00,0x0,0x0,0x04]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + print ("\nStarting putscom test") + testUtil.writeUsFifo( PUTSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOM_EXPDATA ) + testUtil.readEot( ) + print ("\nStarting invalid putscom test") + testUtil.writeUsFifo( PUTSCOM_TESTDATA_INVALID ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOM_EXPDATA_INVALID ) + testUtil.readEot( ) + print ("\nStarting getscom test") + testUtil.writeUsFifo( GETSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETSCOM_EXPDATA ) + testUtil.readEot( ) + print ("\nStarting invalid getscom test") + testUtil.writeUsFifo( GETSCOM_TESTDATA_INVALID ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETSCOM_EXPDATA_INVALID ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutMem.py b/src/test/testcases/testPutMem.py new file mode 100644 index 00000000..cb0398ff --- /dev/null +++ b/src/test/testcases/testPutMem.py @@ -0,0 +1,83 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutMem.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 4 + +PUTMEM_TEST_HDR = [0,0,0,0x86, + 0,0,0xA4,0x02, + 0,0,0x0,0x02, + 0,0,0,0, + 0x08,0x00,0x00,0x00, + 0x00,0x00,0x00,0x80] + +PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01, + 0xAB,0xCD,0xEF,0x02, + 0xAB,0xCD,0xEF,0x03, + 0xAB,0xCD,0xEF,0x04, + 0xAB,0xCD,0xEF,0x05, + 0xAB,0xCD,0xEF,0x06, + 0xAB,0xCD,0xEF,0x07, + 0xAB,0xCD,0xEF,0x08] + +PUTMEM_EXPDATA = [0x00,0x00,0x00,0x80, + 0xc0,0xde,0xa4,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + testUtil.writeUsFifo( PUTMEM_TEST_HDR ) + + loop = 1 + while (loop <= LOOP_COUNT): + #testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( PUTMEM_TEST_DATA ) + loop += 1 + testUtil.writeEot( ) + + #testUtil.runCycles( 10000000 ) + testUtil.readDsFifo( PUTMEM_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutMem_fail.py b/src/test/testcases/testPutMem_fail.py new file mode 100644 index 00000000..a3ab46b5 --- /dev/null +++ b/src/test/testcases/testPutMem_fail.py @@ -0,0 +1,84 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutMem_fail.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 4 + +PUTMEM_TEST_HDR = [0,0,0x00,0x86, + 0,0,0xA4,0x02, + 0,0,0x0,0x02, + 0,0,0,0, + 0x08,0x00,0x00,0x04, # Un-aligned PBA Address + 0x00,0x00,0x00,0x80] + +PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01, + 0xAB,0xCD,0xEF,0x02, + 0xAB,0xCD,0xEF,0x03, + 0xAB,0xCD,0xEF,0x04, + 0xAB,0xCD,0xEF,0x05, + 0xAB,0xCD,0xEF,0x06, + 0xAB,0xCD,0xEF,0x07, + 0xAB,0xCD,0xEF,0x08] + +PUTMEM_EXPDATA = [0x00,0x00,0x00,0x00, + 0xc0,0xde,0xa4,0x02, + 0x00,0xfe,0x00,0x0a, + 0xff,0xdc,0x00,0x03, + 0x00,0x00,0x00,0x00, + 0x00,0xf8,0x82,0x19, + 0x00,0x00,0x00,0x06] + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + testUtil.writeUsFifo( PUTMEM_TEST_HDR ) + + loop = 1 + while (loop <= LOOP_COUNT): + testUtil.writeUsFifo( PUTMEM_TEST_DATA ) + loop += 1 + testUtil.writeEot( ) + + testUtil.readDsFifo( PUTMEM_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testPutScomUnderMask.py b/src/test/testcases/testPutScomUnderMask.py new file mode 100755 index 00000000..b3484bef --- /dev/null +++ b/src/test/testcases/testPutScomUnderMask.py @@ -0,0 +1,98 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testPutScomUnderMask.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +PUTSCOM_TESTDATA = [0,0,0,6, + 0,0,0xA2,0x02, + 0,0,0x0,0x00, + 0,0x05,0x00,0x3E, #scratch reg 7 (32-bit) + 0xff,0xff,0xff,0xff, + 0x00,0x00,0x00,0x00 ] + +PUTSCOM_EXPDATA = [0xc0,0xde,0xa2,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +PUTSCOMUMASK_TESTDATA = [0,0,0,8, + 0,0,0xA2,0x04, + 0,0,0x0,0x00, + 0,0x05,0x00,0x3E, + 0xde,0xca,0xff,0xee, + 0x00,0x00,0x00,0x00, + 0xff,0x00,0xff,0x00, + 0x00,0x00,0x00,0x00] + + +PUTSCOMUMASK_EXPDATA = [0xc0,0xde,0xa2,0x04, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +GETSCOMUMASK_TESTDATA = [0,0,0,4, + 0,0,0xA2,0x01, + 0,0,0x0,0x00, + 0,0x05,0x0,0x3E] + +GETSCOMUMASK_EXPDATA = [0xde, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, + 0xc0,0xde,0xa2,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + testUtil.writeUsFifo( PUTSCOM_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOM_EXPDATA ) + testUtil.readEot( ) + + testUtil.writeUsFifo( PUTSCOMUMASK_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( PUTSCOMUMASK_EXPDATA ) + testUtil.readEot( ) + + testUtil.writeUsFifo( GETSCOMUMASK_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( GETSCOMUMASK_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testRegAccess.xml b/src/test/testcases/testRegAccess.xml new file mode 100755 index 00000000..c5876c0b --- /dev/null +++ b/src/test/testcases/testRegAccess.xml @@ -0,0 +1,46 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testRegAccess.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testStopInstruction.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegGpr.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegFpr.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetRegSpr.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testStartInstruction.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testRegistry.py b/src/test/testcases/testRegistry.py new file mode 100644 index 00000000..dc15fc87 --- /dev/null +++ b/src/test/testcases/testRegistry.py @@ -0,0 +1,79 @@ +#!/usr/bin/python +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testRegistry.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +''' +############################################################# +# @file testClass.py +# @author: George Keishing <gkeishin@in.ibm.com> +# @brief Framework class Host SBE interface on simics +# +# Created on March 29, 2016 +# ---------------------------------------------------- +# @version Developer Date Description +# ---------------------------------------------------- +# 1.0 gkeishin 29/03/16 Initial create +############################################################# +''' + +# Test OP keywords for reference +''' + - read : Read from a Registry + - write : write to a Registry + - memRead : Read from a memory address block +''' + +# Registry address for direct usage +REG_MBOX0 = 0x00680500 +REG_MBOX1 = 0x00680510 +REG_MBOX2 = 0x00680520 +REG_MBOX3 = 0x00680530 +REG_MBOX4 = 0x00680540 +REG_MBOX5 = 0x00680550 +REG_MBOX6 = 0x00680560 +REG_MBOX7 = 0x00680570 + +# PSU doorbell regs +PSU_SBE_DOORBELL_REG = 0x00680600 +PSU_SBE_DOORBELL_REG_WO_AND = 0x00680610 +PSU_SBE_DOORBELL_REG_WO_OR = 0x00680620 + +PSU_HOST_DOORBELL_REG = 0x00680630 +PSU_HOST_DOORBELL_REG_WO_AND = 0x00680640 +PSU_HOST_DOORBELL_REG_WO_OR = 0x00680650 + + +# Memory space address +''' +simics> system_cmp0.phys_mem.map + Base Object Fn Offset Length +------------------------------------------------------------------------- +0x0000008000000 p9Proc0.l3_cache_ram 0 0x0 0xa00000 + width 8192 bytes +0x6030000000000 p9Proc0.lpcm 0 0x6030000000000 0xffffffff + width 4 bytes +0x603fc00000000 proc_p9chip0.mc_freeze 0 0x0 0x400000000 + target -> proc_p9chip0.xscom_memspc, width 8 bytes + +''' +MEM_ADDR = 0x0000008000000 diff --git a/src/test/testcases/testSbeDump.py b/src/test/testcases/testSbeDump.py new file mode 100644 index 00000000..7d7a7d77 --- /dev/null +++ b/src/test/testcases/testSbeDump.py @@ -0,0 +1,110 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testSbeDump.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest") +import testUtil +err = False +#from testWrite import * + +TESTDATA = [0, 0, 0, 3, + 0, 0, 0xA1, 0x01, + 0, 0x02, 0x00, 0x2] + +EXPDATA = [0xc0, 0xde, 0xa1, 0x01] + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main(): + testUtil.runCycles(10000000) + testUtil.writeUsFifo(TESTDATA) + testUtil.writeEot() + testUtil.readDsFifo(EXPDATA) + #flush out primary and secondary status + data = testUtil.readDsEntryReturnVal() + + #flush hwp ffdc + data = testUtil.readDsEntryReturnVal() + data = testUtil.readDsEntryReturnVal() + + #start processing sbe ffdc + data = testUtil.readDsEntryReturnVal() + magicBytes = ((data[0] << 8) | data[1]) + if (magicBytes == 0xFFDC) : + print ("\nMagic Bytes Match") + else : + raise Exception('data mistmach') + packLen = ((data[2] << 8) | data[3]) + print ("\nFFDC package length = " + str(packLen)) + + data = testUtil.readDsEntryReturnVal() + fapiRc = ((data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]) + print ("\nFAPI rc = " + str(hex(fapiRc))) + + data = testUtil.readDsEntryReturnVal() + primaryStatus = ((data[0] << 8) | data[1]) + secondaryStatus = ((data[2] << 8) | data[3]) + print ("\nPrimary Status " + str(hex(primaryStatus)) + " Secondary Status "\ + + str(hex(secondaryStatus))) + + data = testUtil.readDsEntryReturnVal() + header = ((data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]) + print ("\nHeader = " + str(hex(header))) + + for i in range(0, (bin(header).count("1"))): + #read user data id + data = testUtil.readDsEntryReturnVal() + id = (data[0] << 8) | data[1] + print "User data Id ["+str(hex(id))+"]" + len = (data[2] << 8) | data[3] + #if it is trace field SBE_FFDC_TRACE_DUMP + fileName = "" + if(id == 0x0002): + fileName = "trace.bin" + print ("\nlength of trace dump " + str(len)) + #if it is trace field SBE_FFDC_ATTR_DUMP + elif(id == 0x0001): + fileName = "attr.bin" + print ("\nlength of attr dump " + str(len)) + myBin = open(fileName, 'wb') + print ("\nwriting "+fileName) + loopCount = (len ) / 4 + for j in range(0, loopCount): + data = testUtil.readDsEntryReturnVal() + myBin.write(bytearray(data)) + print("write to a file Done") + myBin.close() + #flush out distance + data = testUtil.readDsEntryReturnVal() +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testScom.xml b/src/test/testcases/testScom.xml new file mode 100755 index 00000000..6f59c7cd --- /dev/null +++ b/src/test/testcases/testScom.xml @@ -0,0 +1,42 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testScom.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutScomUnderMask.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testModifyScom.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetInScom.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + diff --git a/src/test/testcases/testSram.py b/src/test/testcases/testSram.py new file mode 100644 index 00000000..ca064c77 --- /dev/null +++ b/src/test/testcases/testSram.py @@ -0,0 +1,129 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testSram.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + +PUTSRAM_OCC_CNTLDATA = [0,0,0,0x20, + 0,0,0xa4,0x04, #magic + 0,0,0,0x01, + 0xe7,0xf0,0x00,0x00, #addr + 0,0,0x01,0x00] # length + +PUTSRAM_OCC_TESTDATA = [0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9, + 0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9] + +PUTSRAM_OCC_EXP_CNTLDATA = [0,0,0x01,0x00, + 0xc0,0xde,0xa4,0x04, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +GETSRAM_OCC_CNTLDATA = [0,0,0,0x5, + 0,0,0xa4,0x03, + 0,0,0,0x01, + 0xe7,0xf0,0x00,0x00, #address + 0x00,0x00,0x01,0x00] # length of data + +GETSRAM_OCC_EXP_TESTDATA = [0xab,0xcd,0xef,0x12, #data + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9, + 0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9] + +GETSRAM_OCC_EXP_CNTLDATA = [0x00,0x00,0x01,0x00, # length + 0xc0,0xde,0xa4,0x03, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # Put Occ Sram test - Linear - Can be tested over Normal + # Debug mode + testUtil.writeUsFifo( PUTSRAM_OCC_CNTLDATA ) + # Write 32 bytes of data 8 times => 32*8 = 256 = 0x100 + i_cnt = 0 + while i_cnt < 8: + testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA ) + i_cnt = i_cnt+1 + + testUtil.writeEot( ) + + # Read the expected data for put sram + testUtil.readDsFifo( PUTSRAM_OCC_EXP_CNTLDATA ) + testUtil.readEot( ) + + # Get Sram Linear + testUtil.writeUsFifo( GETSRAM_OCC_CNTLDATA ) + testUtil.writeEot( ) + + # Read the Expected Data for get Sram + i_cnt = 0 + while i_cnt < 8: + testUtil.readDsFifo( GETSRAM_OCC_EXP_TESTDATA ) + i_cnt = i_cnt+1 + + testUtil.readDsFifo( GETSRAM_OCC_EXP_CNTLDATA ) + testUtil.readEot( ) + + # Put Occ Sram test - Circular - Can be enabled once we get + # valid address range to read the circular data + #testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA_1 ) + #testUtil.writeEot( ) + #testUtil.readDsFifo( PUTSRAM_OCC_EXPDATA_1 ) + #testUtil.readEot( ) + #testUtil.writeUsFifo( GETSRAM_OCC_TESTDATA_1 ) + #testUtil.writeEot( ) + #testUtil.readDsFifo( GETSRAM_OCC_EXPDATA_1 ) + #testUtil.readEot( ) + + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testSram.xml b/src/test/testcases/testSram.xml new file mode 100755 index 00000000..a1e74162 --- /dev/null +++ b/src/test/testcases/testSram.xml @@ -0,0 +1,31 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testSram.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <!-- TODO RTC - 150091 - Add the Occ sram test case --> + <!--<simcmd>run-python-file targets/p9_nimbus/sbeTest/testSram.py</simcmd>--> + <!--<exitonerror>yes</exitonerror>--> + </testcase> + diff --git a/src/test/testcases/testStartInstruction.py b/src/test/testcases/testStartInstruction.py new file mode 100644 index 00000000..cc5cba02 --- /dev/null +++ b/src/test/testcases/testStartInstruction.py @@ -0,0 +1,64 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testStartInstruction.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + + +# Start All thread in Core0 with warn flag true +INST_START0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf0] + +INST_EXPDATA = [0xc0,0xde,0xa7,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + #stop all thread in core0 + testUtil.writeUsFifo( INST_START0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testStopInstruction.py b/src/test/testcases/testStopInstruction.py new file mode 100644 index 00000000..37d79acf --- /dev/null +++ b/src/test/testcases/testStopInstruction.py @@ -0,0 +1,64 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testStopInstruction.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + + +# Stop All thread in Core0 with warn flag true +INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG = [0,0,0,0x03, + 0,0,0xa7,0x01, + 0,1,0x20,0xf1] + +INST_EXPDATA = [0xc0,0xde,0xa7,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + #stop all thread in core0 + testUtil.writeUsFifo( INST_STOP0_ALL_TESTDATA_WITH_WARN_FLG ) + testUtil.writeEot( ) + testUtil.readDsFifo( INST_EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testUtil.py b/src/test/testcases/testUtil.py new file mode 100644 index 00000000..2312d2b7 --- /dev/null +++ b/src/test/testcases/testUtil.py @@ -0,0 +1,170 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testUtil.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import time +import conf +from sim_commands import * + +#err = False +lbus = conf.p9Proc0.proc_lbus_map +def writeUsFifo( data): + """Main test Loop""" + loopCount = len(data)/4; + for i in range (loopCount): + idx = i * 4; + writeEntry(lbus, 0x2400, (data[idx], data[idx+1], data[idx+2], data[idx+3]) ) + +def readDsFifo(data): + """Main test Loop""" + loopCount = len(data)/4; + for i in range (loopCount): + idx = i * 4; + checkEqual(readEntry(lbus, 0x2440, 4), (data[idx], data[idx+1], data[idx+2], data[idx+3])) + +def writeEot(): + write(lbus, 0x2408, (0, 0, 0, 1) ) + +def write(obj, address, value ): + """ Write to memory space """ + iface = SIM_get_interface(obj, "memory_space") + iface.write(None, address, value, 0x0) + +def readEot(): + """ Read from memory space """ + status = read(lbus, 0x2444, 4) + checkEqual( (status[3] & 0x80), 0x80 ); + read(lbus, 0x2440, 4) + +def resetFifo(): + write(lbus, 0x240C, (0, 0, 0, 1)) + return + +def readUsFifoStatus(): + status = read(lbus, 0x2404, 4) + return status + +def readDsFifoStatus(): + status = read(lbus, 0x2444, 4) + return status + +def waitTillFifoEmpty(func): + count = 0 + loop = True + while(loop is True): + status = func() + if(status[1] == 0x10): + loop = False + break + else: + count = count + 1 + runCycles(200000) + if(count > 10): + raise Exception('Timed out waiting for FIFO to get flushed') + + +def waitTillUsFifoEmpty(): + try: + waitTillFifoEmpty(readUsFifoStatus) + except: + raise Exception('US FIFO did not get empty') + + +def waitTillDsFifoEmpty(): + try: + waitTillFifoEmpty(readDsFifoStatus) + except: + raise Exception('DS FIFO did not get empty') + + +# This function will only read the entry but will not compare it +# with anything. This can be used to flush out enteries. +def readDsEntry(entryCount): + for i in range (entryCount): + readEntry(lbus, 0x2440, 4) + +def writeEntry(obj, address, value ): + + loop = 1; + count = 0; + while( loop ): + status = read(lbus, 0x2404, 4) # Address 0x2404: Upstream Fifo Status + + if( status[2] & 0x02): + count = count + 1 + runCycles(200000) + # This will cause test to fail + if(count > 10): + raise Exception('Timeout. FIFO FULL'); + else: + # write entry + write(obj, address, value) + loop = 0 + + return value +def readDsEntryReturnVal(): + data = readEntry(lbus, 0x2440, 4) + runCycles(200000) + return data +def readEntry(obj, address, size): + + """ Read from memory space """ + loop = 1; + count = 0; + value = (0,0,0,0) + while( loop ): + status = read(lbus, 0x2444, 4) # Address 0x2444: Downstream Fifo Status + + if( status[1] & 0x0F): + # read entry + value = read(lbus, address, size) + loop = 0 + else: + count = count + 1 + runCycles(200000) + # This will cause test to fail + if(count > 10): + raise Exception('Timeout. Empty FIFO'); + + return value + +def read(obj, address, size): + """ Read from memory space """ + iface = SIM_get_interface(obj, "memory_space") + value = iface.read(None, address, size, 0x0) + return value + +def runCycles( cycles ): + if (not SIM_simics_is_running()): + syscmd = "run-cycles %d"%(cycles) + ( rc, out ) = quiet_run_command( syscmd, output_modes.regular ) + if ( rc ): + print "simics ERROR running %s: %d "%( syscmd, rc ) + +def checkEqual( data, expdata ): + """ Throw exception if data is not equal """ + if( cmp(data, expdata )): + print "Eqality check failed" + print "Data:", data + print "Expected Data", expdata + raise Exception('data mistmach'); + |
