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| author | Raja Das <rajadas2@in.ibm.com> | 2016-09-27 13:01:28 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-11 01:22:24 -0500 |
| commit | 87d632d8a957d0a2714b93a66650501e02e866a2 (patch) | |
| tree | 56e0958a0b974c2a539b95dbbaac5fd58ccdcfe3 /src/test/testcases/testIstepInvalidFenced.py | |
| parent | f51f14d9f23521f57d41a527c6a0298f4b8baaee (diff) | |
| download | talos-sbe-87d632d8a957d0a2714b93a66650501e02e866a2.tar.gz talos-sbe-87d632d8a957d0a2714b93a66650501e02e866a2.zip | |
MPIPL Start Chipops and Mpipl istep implementation
Change-Id: If0579dfdfb10eb42bc837107e38361512a416b03
RTC: 123696
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30367
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test/testcases/testIstepInvalidFenced.py')
| -rwxr-xr-x | src/test/testcases/testIstepInvalidFenced.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/testcases/testIstepInvalidFenced.py b/src/test/testcases/testIstepInvalidFenced.py index 51b71c11..57a9bdf7 100755 --- a/src/test/testcases/testIstepInvalidFenced.py +++ b/src/test/testcases/testIstepInvalidFenced.py @@ -33,7 +33,7 @@ TESTDATA = [0,0,0,3, 0,0x02,0x00,0x1] EXPDATA = [0xc0,0xde,0xa1,0x01, - 0x00,0x00,0x00,0x08, + 0x00,0x02,0x00,0x0A, 0x00,0x0,0x0,0x03]; # MAIN Test Run Starts Here... @@ -42,6 +42,7 @@ def main( ): testUtil.runCycles( 10000000 ) testUtil.writeUsFifo( TESTDATA ) testUtil.writeEot( ) + testUtil.runCycles( 10000000 ) testUtil.readDsFifo( EXPDATA ) testUtil.readEot( ) #------------------------------------------------- |
