IO, FBC updates to enable ABUS for Fleetwood

Attributes:
-------------------------------------------------------------------------------

nest_attributes.xml
  add ATTR_LINK_TRAIN, written by platform on X, O endpoints to specify
    whether half or full link should be trained
  add ATTR_PROC_FABRIC_LINK_ACTIVE, written by p9_fbc_eff_config_links
  adjust enums for ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG, written
    by p9_fbc_eff_config_links
  add ATTR_PROC_FABRIC_[XA]_LINKS_CNFG, written by p9_fbc_eff_config_links

pervasive_attributes.xml
  create ATTR_PROC_NPU_REGION_ENABLED to encapsulate accessibility of
    NPU logic domain, written by p9_chiplet_scominit

chip_ec_attributes.xml
  add EC feature attribute controlling DL training workaround

Initfiles:
-------------------------------------------------------------------------------

p9.fbc.ab_hp.scom.initfile
  add logic to permit reset of chg_rate master dials in second phase SMP build
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums

p9.fbc.cd_hp.scom.initfile
p9.fbc.no_hp.scom.initfile
  consume number of configured X/A links from new attribute, simple addition
    won't work any longer given new ATTACHED_CHIP_CNFG enums

p9.fbc.ioe_dl.scom.initfile
  support half-link operation, based on ATTR_LINK_TRAIN on X endpoint target

p9.fbc.ioe_tl.scom.initifle
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums

p9.fbc.ioo_dl.scom.initfile
  support half-link operation, based on ATTR_LINK_TRAIN on O endpoint target
  qualify OLL enablement based on use as active fabric link
  adjust PHY training parameters based on current lab learning

p9.fbc.ioo_tl.scom.initfile
  adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
  support half-link operation, based on ATTACHED_CHIP_CNFG
  qualify TOD_ENABLE to apply only to O links carrying X traffic

p9.npu.scom.initfile
  clear OPTICAL_IO_CONFIG when not actively using NVLINK, finer-grained
    updates needed to support mix of O SMP and NVLINK usage

HWPs:
-------------------------------------------------------------------------------

p9_io_obus_dccal
  execute only on links actively carrying fabric protocol

p9_io_obus_linktrain
p9_io_regs
  encapsulate PHY FIFO reset sequence needed prior to FBC DL training execution

p9_chiplet_scominit
p9_npu_scominit
  partial good updates for NPU region

p9_fab_iovalid
  adjust iovalid manipulation/checking, as well as link delay reporting, to
    support half-link configuration

p9_smp_link_layer
  support half-link configuration via ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG
  implement OBUS PHY specific workarounds

p9_eff_config_links
  update ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG to support half-link
    configuration
  write ATTR_PROC_FABRIC_LINK_ACTIVE on X/O endpoint targets
  write ATTR_PROC_FABRIC_[XA]_LINKS_CNFG to reflect total number of logically
    configured links, for initfile consumption

Istep wrappers:
-------------------------------------------------------------------------------

p9_build_smp_wrap
  correctly loop over all system targets for second phase SMP build

p9_sys_chiplet_scominit_wrap
  initial release

Change-Id: Ic1d87df4d3ff0feca7ac2437fa61b6d2fc4a2d68
CQ: HW419022
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46996
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

0 files changed, 0 insertions, 0 deletions