PHB getFunctional to be modified based on the IOVALID bit

Change-Id: I1efd3ac514b5efb0c83e7a0eeb4581a6deb02a18
RTC: SW392452
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42270
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 27 insertions, 22 deletions

diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index 3aafcae5..7c80790c 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -1385,36 +1385,41 @@ ReturnCode updatePhbFunctionalState( void )
     const uint64_t pci_cplt_conf1[3] = {PEC_0_CPLT_CONF1, PEC_1_CPLT_CONF1, PEC_2_CPLT_CONF1};
 
     Target<TARGET_TYPE_PROC_CHIP > procTgt = plat_getChipTarget();
-    auto phbTgt = procTgt.getChildren<fapi2::TARGET_TYPE_PHB>();
+    auto phbTgt_vec = procTgt.getChildren<fapi2::TARGET_TYPE_PHB>();
 
-    uint8_t phbCnt = 0;
-    for (uint8_t pciCnt=0; pciCnt<3; pciCnt++)
+    for (auto &phbTgt : phbTgt_vec)
     {
-        uint64_t data = 0;
+        //Get the PHB id
+        uint8_t phb_id = 0;
+        uint8_t pci_id = 0;
         uint8_t phbPerPciCnt = 0;
-
-        rc = getscom_abs_wrap (&procTgt, pci_cplt_conf1[pciCnt], &data);
+        uint64_t data = 0;
+       
+        FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, phbTgt, phb_id);
+        if(phb_id == 1 || phb_id == 2)
+        {
+            pci_id = 1;
+            phbPerPciCnt = phb_id - 1; // To rotate per phb cnt within PCI from 0 to 1
+        }
+        else if(phb_id > 2)
+        {
+            pci_id = 2;
+            phbPerPciCnt = phb_id - 3; // To rotate per phb cnt within PCI from 0 to 1
+        }
+        rc = getscom_abs_wrap (&procTgt, pci_cplt_conf1[pci_id], &data);
         if(rc != FAPI2_RC_SUCCESS)
         {
-            SBE_ERROR(SBE_FUNC" Failed to read Pec[%d] Chiplet Config1 register",pciCnt);
+            SBE_ERROR(SBE_FUNC" Failed to read Pec[%d] Chiplet Config1 register",pci_id);
             break;
         }
-
-        do
+        // Fetch bit4 from D000009 for PHB0
+        // Fetch bit4/5 from E000009 for PHB1/2
+        // Fetch bit4/5/6 from F000009 for PHB3/4/5
+        if( !((data >> (PEC_PHB_IOVALID_BIT_SHIFT - phbPerPciCnt)) & PEC_PHB_IOVALID_BIT_MASK) )
         {
-            // Fetch bit4 from D000009 for PHB0
-            // Fetch bit4/5 from E000009 for PHB1/2
-            // Fetch bit4/5/6 from F000009 for PHB3/4/5
-            if( ((data >> (PEC_PHB_IOVALID_BIT_SHIFT - phbPerPciCnt)) &
-                        PEC_PHB_IOVALID_BIT_MASK) )
-            {
-                static_cast<plat_target_handle_t&>(phbTgt[phbCnt++].operator ()()).setFunctional(true);
-            }
-            else
-            {
-                static_cast<plat_target_handle_t&>(phbTgt[phbCnt++].operator ()()).setFunctional(false);
-            }
-        }while(++phbPerPciCnt<=pciCnt);
+            SBE_INFO(SBE_FUNC "PHB[%d] setting up as Non-Functional", phb_id);
+            static_cast<plat_target_handle_t&>(phbTgt.operator ()()).setFunctional(false);
+        }
     }
 
     SBE_EXIT(SBE_FUNC);