Added support for async bit

Change-Id: Iff4dd1f50e04ae67072e287d89ab098a9f7545d0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42067
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 77 insertions, 38 deletions

diff --git a/src/sbefw/sbecmdcntrldmt.C b/src/sbefw/sbecmdcntrldmt.C
index 3cf26b83..5fc248b3 100644
--- a/src/sbefw/sbecmdcntrldmt.C
+++ b/src/sbefw/sbecmdcntrldmt.C
@@ -80,6 +80,7 @@ void sbeDmtPkExpiryCallback(void *)
         SBE_ERROR(SBE_FUNC "PutScom failed for REG PERV_N3_LOCAL_FIR");
         pk_halt();
     }
+    (void)SbeRegAccess::theSbeRegAccess().updateAsyncFFDCBit(true);
     // TODO - Store the response in Async Response
     // RTC:149074
     #undef SBE_FUNC
diff --git a/src/sbefw/sbecmdgeneric.C b/src/sbefw/sbecmdgeneric.C
index c2cf53cc..49b493c5 100644
--- a/src/sbefw/sbecmdgeneric.C
+++ b/src/sbefw/sbecmdgeneric.C
@@ -214,6 +214,13 @@ uint32_t sbeGetFfdc (uint8_t *i_pArg)
         }
         rc = sbeDsSendRespHdr(respHdr);
 
+        if (rc)
+        {
+            break;
+        }
+        // If we are able to send ffdc, turn off asny ffdc bit
+        (void)SbeRegAccess::theSbeRegAccess().updateAsyncFFDCBit(false);
+
     }while(0);
 
     if( rc )
diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index 6e1b4e3e..2d946008 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -933,6 +933,8 @@ void sbeDoContinuousIpl()
                     SBE_ERROR(SBE_FUNC"Failed istep execution in plck mode: "
                             "Major: %d, Minor: %d", l_major, l_minor);
                     l_done = true;
+                    (void)SbeRegAccess::theSbeRegAccess().updateAsyncFFDCBit(
+                                                                          true);
                     break;
                 }
                 // Check if we are at step 3.20 on the slave SBE
diff --git a/src/sbefw/sberegaccess.C b/src/sbefw/sberegaccess.C
index 76871528..0550fa28 100644
--- a/src/sbefw/sberegaccess.C
+++ b/src/sbefw/sberegaccess.C
@@ -135,7 +135,7 @@ uint32_t SbeRegAccess::init()
 {
     #define SBE_FUNC "SbeRegAccess::SbeRegAccess "
     static bool l_initDone = false;
-    uint32_t l_rc = 0;
+    uint32_t rc = 0;
     uint64_t l_mbx8 = 0;
     do
     {
@@ -144,30 +144,30 @@ uint32_t SbeRegAccess::init()
             break;
         }
         // Read SBE messaging register into iv_messagingReg
-        l_rc = getscom_abs(PERV_SB_MSG_SCOM, &iv_messagingReg);
-        if(PCB_ERROR_NONE != l_rc)
+        rc = getscom_abs(PERV_SB_MSG_SCOM, &iv_messagingReg);
+        if(PCB_ERROR_NONE != rc)
         {
             SBE_ERROR(SBE_FUNC"Failed reading sbe messaging reg., RC: 0x%08X. ",
-                      l_rc);
+                      rc);
             break;
         }
         // Read Mailbox register 8 to check if the mailbox registers 3 and 6 are
         // valid
-        l_rc = getscom_abs(PERV_SCRATCH_REGISTER_8_SCOM, &l_mbx8);
-        if(PCB_ERROR_NONE != l_rc)
+        rc = getscom_abs(PERV_SCRATCH_REGISTER_8_SCOM, &l_mbx8);
+        if(PCB_ERROR_NONE != rc)
         {
             SBE_ERROR(SBE_FUNC"Failed reading mailbox reg 7, RC: 0x%08X. ",
-                      l_rc);
+                      rc);
             break;
         }
         if(l_mbx8 & SBE_MBX8_MBX3_VALID_MASK)
         {
             // Read MBX3
-            l_rc = getscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, &iv_mbx3);
-            if(PCB_ERROR_NONE != l_rc)
+            rc = getscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, &iv_mbx3);
+            if(PCB_ERROR_NONE != rc)
             {
                 SBE_ERROR(SBE_FUNC"Failed reading mailbox reg 3, RC: 0x%08X. ",
-                        l_rc);
+                        rc);
                 break;
             }
         }
@@ -182,11 +182,11 @@ uint32_t SbeRegAccess::init()
         if(l_mbx8 & SBE_MBX8_MBX6_VALID_MASK)
         {
             // Read MBX6
-            l_rc = getscom_abs(PERV_SCRATCH_REGISTER_6_SCOM, &iv_mbx6);
-            if(PCB_ERROR_NONE != l_rc)
+            rc = getscom_abs(PERV_SCRATCH_REGISTER_6_SCOM, &iv_mbx6);
+            if(PCB_ERROR_NONE != rc)
             {
                 SBE_ERROR(SBE_FUNC"Failed reading mailbox reg 6, RC: 0x%08X. "
-                          l_rc);
+                          rc);
                 break;
             }
         }
@@ -195,10 +195,10 @@ uint32_t SbeRegAccess::init()
         // check the C4 board pin to determine role
         // Read device ID register
         uint64_t l_sbeDevIdReg = 0;
-        l_rc = getscom_abs(PERV_DEVICE_ID_REG, &l_sbeDevIdReg);
-        if(PCB_ERROR_NONE != l_rc)
+        rc = getscom_abs(PERV_DEVICE_ID_REG, &l_sbeDevIdReg);
+        if(PCB_ERROR_NONE != rc)
         {
-            SBE_ERROR(SBE_FUNC"Failed reading device id reg, RC: 0x%08X.",l_rc);
+            SBE_ERROR(SBE_FUNC"Failed reading device id reg, RC: 0x%08X.",rc);
             break;
         }
 
@@ -216,7 +216,7 @@ uint32_t SbeRegAccess::init()
               "mbx6: 0x%08X", (uint32_t)(l_mbx8 >> 32),
               (uint32_t)(iv_mbx3 >> 32), (uint32_t)(iv_mbx6 >> 32));
     l_initDone = true;
-    return l_rc;
+    return rc;
     #undef SBE_FUNC
 }
 
@@ -234,17 +234,17 @@ uint32_t SbeRegAccess::init()
 uint32_t SbeRegAccess::updateSbeState(const sbeState &i_state)
 {
     #define SBE_FUNC "SbeRegAccess::updateSbeState "
-    uint32_t l_rc = 0;
+    uint32_t rc = 0;
 
     iv_prevState = iv_currState;
     iv_currState = i_state;
-    l_rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
-    if(PCB_ERROR_NONE != l_rc)
+    rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
+    if(PCB_ERROR_NONE != rc)
     {
         SBE_ERROR(SBE_FUNC"Failed to update state to messaging "
-                "register. RC: 0x%08X", l_rc);
+                "register. RC: 0x%08X", rc);
     }
-    return l_rc;
+    return rc;
     #undef SBE_FUNC
 }
 
@@ -263,18 +263,18 @@ uint32_t SbeRegAccess::updateSbeStep(const uint8_t i_major,
                                      const uint8_t i_minor)
 {
     #define SBE_FUNC "SbeRegAccess::updateSbeStep "
-    uint32_t l_rc = 0;
+    uint32_t rc = 0;
 
     iv_majorStep = i_major;
     iv_minorStep = i_minor;
 
-    l_rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
-    if(l_rc)
+    rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
+    if(rc)
     {
         SBE_ERROR(SBE_FUNC"Failed to update SBE step to messaging "
-                "register. RC: 0x%08X", l_rc);
+                "register. RC: 0x%08X", rc);
     }
-    return l_rc;
+    return rc;
     #undef SBE_FUNC
 }
 
@@ -290,16 +290,16 @@ uint32_t SbeRegAccess::updateSbeStep(const uint8_t i_major,
 uint32_t SbeRegAccess::setSbeReady()
 {
     #define SBE_FUNC "SbeRegAccess::setSbeReady "
-    uint32_t l_rc = 0;
+    uint32_t rc = 0;
 
     iv_sbeBooted = true;
-    l_rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
-    if(l_rc)
+    rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
+    if(rc)
     {
         SBE_ERROR(SBE_FUNC"Failed to update SBE ready state to "
-                "messaging register. RC: 0x%08X", l_rc);
+                "messaging register. RC: 0x%08X", rc);
     }
-    return l_rc;
+    return rc;
     #undef SBE_FUNC
 }
 
@@ -317,17 +317,34 @@ uint32_t SbeRegAccess::setSbeReady()
 uint32_t SbeRegAccess::setMpIplMode(const bool i_set)
 {
     #define SBE_FUNC "SbeRegAccess::setMpIplMode"
-    uint32_t l_rc = 0;
+    uint32_t rc = 0;
     uint8_t l_set = i_set;
     iv_mpiplMode = i_set;
     FAPI_ATTR_SET(ATTR_IS_MPIPL, Target<TARGET_TYPE_SYSTEM>(), l_set);
-    l_rc = putscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, iv_mbx3);
-    if(l_rc)
+    rc = putscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, iv_mbx3);
+    if(rc)
     {
         SBE_ERROR(SBE_FUNC"Failed to set/clear MPIPL flag in "
-                "mbx reg. 3. RC: 0x%08X", l_rc);
+                "mbx reg. 3. RC: 0x%08X", rc);
     }
-    return l_rc;
+    return rc;
+    #undef SBE_FUNC
+}
+
+uint32_t SbeRegAccess::updateAsyncFFDCBit( bool i_on )
+{
+    #define SBE_FUNC "SbeRegAccess::updateAsyncFFDCBit "
+    uint32_t rc = 0;
+
+    iv_asyncFFDC = i_on;
+
+    rc = putscom_abs(PERV_SB_MSG_SCOM, iv_messagingReg);
+    if(rc)
+    {
+        SBE_ERROR(SBE_FUNC"Failed to update SBE Aync bit in message "
+                "register. RC: 0x%08X", rc);
+    }
+    return rc;
     #undef SBE_FUNC
 }
 
diff --git a/src/sbefw/sberegaccess.H b/src/sbefw/sberegaccess.H
index 6dd0065a..49262375 100644
--- a/src/sbefw/sberegaccess.H
+++ b/src/sbefw/sberegaccess.H
@@ -215,6 +215,17 @@ class SbeRegAccess
          */
         void stateTransition(const sbeEvent &i_event);
 
+        /**
+         * @brief Update the async bit into the SBE messaging register. The
+         * function does a read-modify-write, so any bits other than the async
+         * bits are retained.
+         *
+         * @param [in] i_on True to turn on bit, false to turn off
+         *
+         * @return RC indicating success/failure.
+         *
+         */
+        uint32_t updateAsyncFFDCBit( bool i_on );
     private:
 
         /**
@@ -256,7 +267,8 @@ class SbeRegAccess
             struct
             {
                 uint64_t iv_sbeBooted : 1;
-                uint64_t iv_reserved1 : 3;
+                uint64_t iv_asyncFFDC : 1;
+                uint64_t iv_reserved1 : 2;
                 uint64_t iv_prevState : 4;
                 uint64_t iv_currState : 4;
                 uint64_t iv_majorStep : 8; // Max major is 97