Fuse core mode support

Change-Id: I9f034d958ff3a499da623d73badd2ee06565a425
RTC: 166962
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41521
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 126 insertions, 55 deletions

diff --git a/src/sbefw/sbecmdcntrldmt.C b/src/sbefw/sbecmdcntrldmt.C
index 7bbab5b2..3cf26b83 100644
--- a/src/sbefw/sbecmdcntrldmt.C
+++ b/src/sbefw/sbecmdcntrldmt.C
@@ -126,48 +126,90 @@ uint32_t sbeStartCntlDmt()
         (void)SbeRegAccess::theSbeRegAccess().stateTransition(
                                             SBE_DMT_ENTER_EVENT);
 
-        // Fetch the master core
         Target<TARGET_TYPE_PROC_CHIP > l_procTgt = plat_getChipTarget();
-
-        // Fetch the MASTER_CORE attribute
-        uint8_t l_coreId = 0;
-        FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE,l_procTgt,l_coreId);
-
-        // Construct the Master Core Target
-        Target<TARGET_TYPE_CORE> l_coreTgt(
-                plat_getTargetHandleByChipletNumber<TARGET_TYPE_CORE>(
-                    CORE_CHIPLET_OFFSET + l_coreId));
+        // Fetch the Master EX
+        uint8_t exId = 0;
+        uint8_t fuseMode = 0;
+        FAPI_ATTR_GET(fapi2::ATTR_MASTER_EX,l_procTgt,exId);
+        FAPI_ATTR_GET(ATTR_FUSED_CORE_MODE, Target<TARGET_TYPE_SYSTEM>(), fuseMode);
+        fapi2::Target<fapi2::TARGET_TYPE_EX >
+            exTgt(plat_getTargetHandleByInstance<fapi2::TARGET_TYPE_EX>(exId));
 
         // Call Hwp p9_sbe_check_master_stop15 and loop
         // Go around a loop till you get FAPI2_RC_SUCCESS
         do
         {
-            SBE_EXEC_HWP(l_fapiRc, p9_sbe_check_master_stop15_hwp, l_coreTgt);
-            //Conversion is required here, since ReturnCode doesn't support
-            //comparision '!=' or '=='
-            //TODO RTC:149021
-            uint32_t l_rcFapi = l_fapiRc;
-            if( (l_rcFapi != fapi2::RC_CHECK_MASTER_STOP15_PENDING) &&
-                    (l_rcFapi != FAPI2_RC_SUCCESS))
+            //Initilise both core's fapirc with Success, If it's a non-fused
+            //mode then only Core0's fapiRC will get modified below, second
+            //fapiRc will remain Success
+            uint32_t rcFapi[2] = {FAPI2_RC_SUCCESS};
+            uint8_t coreCnt = 0;
+            for (auto &coreTgt : exTgt.getChildren<fapi2::TARGET_TYPE_CORE>())
+            {
+                // Core0 is assumed to be the master core
+                SBE_INFO(SBE_FUNC "Executing p9_sbe_check_master_stop15_hwp for Core[%d]",
+                    coreTgt.get().getTargetInstance());
+                
+                SBE_EXEC_HWP(l_fapiRc, p9_sbe_check_master_stop15_hwp, coreTgt);
+                rcFapi[coreCnt++] = l_fapiRc;
+                if( (l_fapiRc != fapi2::RC_CHECK_MASTER_STOP15_PENDING) &&
+                    (l_fapiRc != FAPI2_RC_SUCCESS))
+                {
+                    SBE_ERROR(SBE_FUNC" p9_sbe_check_master_stop15 returned "
+                        "failure for Core[%d]",coreTgt.get().getTargetInstance());
+                    // Async Response to be stored
+                    // RTC:149074
+                    break;
+                }
+                if(!fuseMode)
+                {
+                    // This is non-fuse mode, so break here, no need to do the
+                    // p9_sbe_check_master_stop15_hwp on second core.
+                    break;
+                }
+            }
+            // Break from do..while(timer.active), if error already happened
+            if( (l_fapiRc != fapi2::RC_CHECK_MASTER_STOP15_PENDING) &&
+                (l_fapiRc != FAPI2_RC_SUCCESS) )
             {
-                SBE_ERROR(SBE_FUNC" p9_sbe_check_master_stop15 "
-                        "returned failure");
-                // Async Response to be stored
-                // RTC:149074
-                break;
+                break; //do..while(timer.active)
             }
 
-            // Only for Pending and Success case
-            if(RC_CHECK_MASTER_STOP15_PENDING != l_rcFapi) // Success
+            // Only for Pending and Success case, 
+            // If non-fuse core mode then single core status is Pending/Success,
+            // if fuse core mode then both core's status is pending/success
+           
+            if(RC_CHECK_MASTER_STOP15_PENDING != rcFapi[0] &&
+                RC_CHECK_MASTER_STOP15_PENDING != rcFapi[1]) // Success
             {
-                SBE_EXEC_HWP(l_fapiRc, p9_block_wakeup_intr_hwp, l_coreTgt,
+                for (auto coreTgt : exTgt.getChildren<fapi2::TARGET_TYPE_CORE>())
+                {
+                    SBE_INFO(SBE_FUNC "Executing p9_block_wakeup_intr_hwp for Core[%d]",
+                        coreTgt.get().getTargetInstance());
+                    SBE_EXEC_HWP(l_fapiRc, p9_block_wakeup_intr_hwp, coreTgt,
                                                 p9pmblockwkup::CLEAR);
-                if( l_fapiRc )
+                    if( l_fapiRc )
+                    {
+                        SBE_ERROR(SBE_FUNC" p9_block_wakeup_intr failed for "
+                            "Core[%d]",coreTgt.get().getTargetInstance());
+                        // TODO via RTC 149074
+                        // Async Response to be stored.
+                        // Also checkstop the system.
+                        break;
+                    }
+                    // If Success for the First core & it's a Fuse core then
+                    // continue here for the Second core then go on to press the
+                    // Door Bell
+                    if(!fuseMode)
+                    {
+                        break;
+                    }
+                }
+                
+                // Break out for the p9_block_wakeup_intr failure above
+                // Dont press the Door bell
+                if(l_fapiRc)
                 {
-                    SBE_ERROR(SBE_FUNC" p9_block_wakeup_intr failed ");
-                    // TODO via RTC 149074
-                    // Async Response to be stored.
-                    // Also checkstop the system.
                     break;
                 }
                 // indicate the Host via Bit SBE_SBE2PSU_DOORBELL_SET_BIT2
@@ -176,7 +218,7 @@ uint32_t sbeStartCntlDmt()
                 if(l_rc)
                 {
                     SBE_ERROR(SBE_FUNC " Failed to Write "
-                            "SBE_SBE2PSU_DOORBELL_SET_BIT2");
+                         "SBE_SBE2PSU_DOORBELL_SET_BIT2");
                 }
                 break; // Breakout from do..while()
             }
diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index 1fe1205e..6a906d9d 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -40,6 +40,7 @@
 #include "sbecmdcntrldmt.H"
 // TODO Workaround
 #include "plat_target_parms.H"
+
 #include "fapi2.H"
 #include "p9_misc_scom_addresses_fld.H"
 // Pervasive HWP Header Files ( istep 2)
@@ -736,26 +737,40 @@ ReturnCode istepCacheInitf (sbeIstepHwp_t i_hwp )
 }
 
 //----------------------------------------------------------------------------
-
 ReturnCode istepWithCore( sbeIstepHwp_t i_hwp)
 {
+    #define SBE_FUNC "istepWithCore"
     ReturnCode rc = FAPI2_RC_SUCCESS;
-    // TODO via RTC 135345
-    // Curently we are passing Hard code core target. Finally it is
-    // going to be a multicast target. Once multicast support is
-    // present, use the right target.
-    fapi2::Target<fapi2::TARGET_TYPE_CORE > coreTgt;
-    // Put this in scope so that vector can be freed up before calling hwp.
+
+    // Get master Ex
+    uint8_t exId = 0;
+    uint8_t fuseMode = 0;
+    Target<TARGET_TYPE_PROC_CHIP > proc = plat_getChipTarget();
+    FAPI_ATTR_GET(fapi2::ATTR_MASTER_EX,proc,exId);
+    FAPI_ATTR_GET(ATTR_FUSED_CORE_MODE, Target<TARGET_TYPE_SYSTEM>(), fuseMode);
+    fapi2::Target<fapi2::TARGET_TYPE_EX >
+        exTgt(plat_getTargetHandleByInstance<fapi2::TARGET_TYPE_EX>(exId));
+    assert( NULL != i_hwp.coreHwp );
+
+    for (auto &coreTgt : exTgt.getChildren<fapi2::TARGET_TYPE_CORE>())
     {
-        Target<TARGET_TYPE_PROC_CHIP > proc = plat_getChipTarget();
-        auto coreList = proc.getChildren<fapi2::TARGET_TYPE_CORE>();
-        // As it is workaround lets assume there will always be atleast one
-        // functional ec. No need to validate.
-        coreTgt = coreList[0];
+        // Core0 is assumed to be the master core
+        SBE_EXEC_HWP(rc, i_hwp.coreHwp, coreTgt)
+        if(rc != FAPI2_RC_SUCCESS)
+        {
+            SBE_ERROR(SBE_FUNC " istepWithCore failed, RC=[0x%08X]", rc);
+            break;
+        }
+        // Only continue in case of istep4 && fuse core mode
+        if(!( (fuseMode) &&
+              (SbeRegAccess::theSbeRegAccess().getSbeMajorIstepNumber() == 
+                                                            SBE_ISTEP4) ) )
+        {
+            break;
+        }
     }
-    assert( NULL != i_hwp.coreHwp );
-    SBE_EXEC_HWP(rc, i_hwp.coreHwp, coreTgt )
     return rc;
+    #undef SBE_FUNC
 }
 
 //----------------------------------------------------------------------------
diff --git a/src/sbefw/sbecmdprocessor.C b/src/sbefw/sbecmdprocessor.C
index 6339268b..e2362a1f 100644
--- a/src/sbefw/sbecmdprocessor.C
+++ b/src/sbefw/sbecmdprocessor.C
@@ -245,7 +245,7 @@ void sbeSyncCommandProcessor_routine(void *i_pArg)
     // Update SBE msgg reg to indicate that control loop
     // is ready now to receive data on its interfaces
     (void)SbeRegAccess::theSbeRegAccess().setSbeReady();
-    
+
     // Check the destination bit at the start
     if(true == SbeRegAccess::theSbeRegAccess().isDestBitRuntime())
     {
diff --git a/src/sbefw/sberegaccess.C b/src/sbefw/sberegaccess.C
index 15f3f0e6..76871528 100644
--- a/src/sbefw/sberegaccess.C
+++ b/src/sbefw/sberegaccess.C
@@ -34,6 +34,7 @@
 #include "fapi2.H"
 #include <ppe42_scom.h>
 #include <p9_perv_scom_addresses.H>
+#include <p9_misc_scom_addresses.H>
 
 using namespace fapi2;
 
@@ -189,19 +190,20 @@ uint32_t SbeRegAccess::init()
                 break;
             }
         }
+
         // If the master/slave bit is 0 (either default or read from mbx6),
         // check the C4 board pin to determine role
+        // Read device ID register
+        uint64_t l_sbeDevIdReg = 0;
+        l_rc = getscom_abs(PERV_DEVICE_ID_REG, &l_sbeDevIdReg);
+        if(PCB_ERROR_NONE != l_rc)
+        {
+            SBE_ERROR(SBE_FUNC"Failed reading device id reg, RC: 0x%08X.",l_rc);
+            break;
+        }
+
         if(0 == iv_isSlave)
         {
-            uint64_t l_sbeDevIdReg = 0;
-            // Read device ID register
-            l_rc = getscom_abs(PERV_DEVICE_ID_REG, &l_sbeDevIdReg);
-            if(PCB_ERROR_NONE != l_rc)
-            {
-                SBE_ERROR(SBE_FUNC"Failed reading device id reg, RC: 0x%08X. "
-                          l_rc);
-                break;
-            }
             iv_isSlave = l_sbeDevIdReg & SBE_DEV_ID_C4_PIN_MASK;
             SBE_INFO(SBE_FUNC"Overriding master/slave with data read from "
                       "C4 pin: HI: 0x%08X, LO: 0x%08X",
diff --git a/src/sbefw/sberegaccess.H b/src/sbefw/sberegaccess.H
index 473370f3..6dd0065a 100644
--- a/src/sbefw/sberegaccess.H
+++ b/src/sbefw/sberegaccess.H
@@ -198,6 +198,17 @@ class SbeRegAccess
         }
 
         /**
+         * @brief Get the SBE major istep number
+         *
+         * @return SBE current major istep number
+         *
+         */
+        uint8_t getSbeMajorIstepNumber() const
+        {
+            return iv_majorStep;
+        }
+
+        /**
          * @brief Update the SBE State as per the transition event
          *
          * @param [in] i_event Transition Event
@@ -261,6 +272,7 @@ class SbeRegAccess
         static const uint64_t SBE_MBX8_MBX3_VALID_MASK = 0x2000000000000000ULL;
         static const uint64_t SBE_MBX8_MBX6_VALID_MASK = 0x0400000000000000ULL;
         static const uint64_t SBE_DEV_ID_C4_PIN_MASK = 0x0000000000800000ULL;
+        static const uint64_t SBE_PERV_DEVICE_ID_REG_BIT58_MASK = 0x0000000000000020ULL;
         static SbeRegAccess cv_instance;
 };
 #endif //__SBEFW_SBEREGACCESS_H