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| author | Yue Du <daviddu@us.ibm.com> | 2016-10-13 09:13:42 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-10 23:52:12 -0500 |
| commit | f51f14d9f23521f57d41a527c6a0298f4b8baaee (patch) | |
| tree | 969e5e21aff43fe34e431d40f793548b73dcc1c0 /src/import | |
| parent | 18e434d4e8e7b7ef2026c0b15905606b414f4304 (diff) | |
| download | talos-sbe-f51f14d9f23521f57d41a527c6a0298f4b8baaee.tar.gz talos-sbe-f51f14d9f23521f57d41a527c6a0298f4b8baaee.zip | |
HB: fix HB core boot resulting cme boot
Change-Id: I18f7c24dc84536126a90a251ae770b0498b5d3d0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31138
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Dev-Ready: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31162
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index a508e448..01c793e6 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -87,6 +87,7 @@ p9_hcd_cache_startclocks( { FAPI_INF(">>p9_hcd_cache_startclocks"); fapi2::buffer<uint64_t> l_qcsr; + fapi2::buffer<uint64_t> l_qssr; fapi2::buffer<uint64_t> l_data64; uint64_t l_region_clock; uint64_t l_l2sync_clock; @@ -137,6 +138,8 @@ p9_hcd_cache_startclocks( if (l_qcsr & BIT64(l_attr_chip_unit_pos << 1)) { + l_qssr |= (BIT64(l_attr_chip_unit_pos << 1) | + BIT64(l_attr_chip_unit_pos + 14)); l_region_clock |= p9hcd::CLK_REGION_EX0_L2_L3_REFR; l_l2sync_clock |= BIT64(36); FAPI_DBG("Sequence EX0 EDRAM enables via QPPM_QCCR[0-3]"); @@ -157,6 +160,8 @@ p9_hcd_cache_startclocks( if (l_qcsr & BIT64((l_attr_chip_unit_pos << 1) + 1)) { + l_qssr |= (BIT64((l_attr_chip_unit_pos << 1) + 1) | + BIT64(l_attr_chip_unit_pos + 14)); l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR; l_l2sync_clock |= BIT64(37); FAPI_DBG("Sequence EX1 EDRAM enables via QPPM_QCCR[4-7]"); @@ -323,6 +328,16 @@ p9_hcd_cache_startclocks( l_data64 = (l_l2pscom_mask | l_l3pscom_mask); FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_data64)); + // ------------------------------- + // Update Status + // ------------------------------- + + FAPI_DBG("Set cache as ready to run in STOP history register"); + FAPI_TRY(putScom(i_target, EQ_PPM_SSHSRC, 0)); + + FAPI_DBG("Set cache as running in QSSR"); + FAPI_TRY(putScom(l_chip, PU_OCB_OCI_QSSR_SCOM1, l_qssr)); + fapi_try_exit: FAPI_INF("<<p9_hcd_cache_startclocks"); |
