diff options
| author | Joachim Fenkes <fenkes@de.ibm.com> | 2018-08-20 17:48:05 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-08-29 08:35:59 -0500 |
| commit | bbce13954daa3ab33287f117e0dc6c2a6bde385c (patch) | |
| tree | 1763665bf390f70eb69eee5cb5a4a08e28b8c5d1 /src/import | |
| parent | 037aa8a374c521a1a820354c416937739563c93c (diff) | |
| download | talos-sbe-bbce13954daa3ab33287f117e0dc6c2a6bde385c.tar.gz talos-sbe-bbce13954daa3ab33287f117e0dc6c2a6bde385c.zip | |
lpc_init: Correct LPC host controller timeout value
The LPC host controller has an interesting way to decode the timeout
value. The left 4 bits are used for the "short wait" timeout, while
the entire 8 bits are used for the "long wait" timeout. If the "short
wait" timeout is 0xF, it is taken to be infinite, causing the host
controller to hang if the slave doesn't respond.
Change the timeout value from 0xFE to 0xEF, the correct maximum value
that is not decoded to be infinity.
Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360
CQ: SW442999
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64856
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H index 91301726..afec9705 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H @@ -61,7 +61,7 @@ extern "C" const uint32_t LPCM_OPB_MASTER_TIMEOUT_REG = 0xC0010040; const uint32_t LPCM_OPB_MASTER_TIMEOUT_VALUE = 0x01312D00; // 50ms at 1600MHz Nest / 400MHz OPB const uint32_t LPCM_LPC_MASTER_TIMEOUT_REG = 0xC001202C; - const uint32_t LPCM_LPC_MASTER_TIMEOUT_VALUE = 0xFE000000; + const uint32_t LPCM_LPC_MASTER_TIMEOUT_VALUE = 0xEF000000; const uint32_t CPLT_CONF1_TC_LP_RESET = 12; fapi2::ReturnCode p9_sbe_lpc_init(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); |
