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| author | Thi Tran <thi@us.ibm.com> | 2017-02-23 14:18:04 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-21 04:34:44 -0400 |
| commit | b530dda701296b221a11333d90c5aa8dcdcd43b7 (patch) | |
| tree | ebc600aa4bf2f08a5e4d4db94005165fb9196e42 /src/import | |
| parent | ddbd1c07f224346b1b0951ee3fd90abfaf135051 (diff) | |
| download | talos-sbe-b530dda701296b221a11333d90c5aa8dcdcd43b7.tar.gz talos-sbe-b530dda701296b221a11333d90c5aa8dcdcd43b7.zip | |
Core Init additions to put ABIST engines in parallel mode for Nimbus DD1.0
CMVC-Prereq:1019352
RTC:167284
Change-Id: I167c63950f72eb0446e3dd746ebd1e12adfb9f69
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36962
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36965
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C index 47780ffb..f76992c4 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,11 +49,15 @@ //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ +// simGETFAC B0.C0.S0.P0.E9.TP.TCEC14.CORE.EPS.CC.COMP.OPCG.LPCNTQ.LATC.L2 43 -ox +//0x000000012B8 +// simGETFAC B0.C0.S0.P0.E9.TP.TCEC14.CORE.EPS.CTRL.COMP.CPLT_STATQ.LATC.L2 24 -ox +//0x804000 enum P9_HCD_CORE_ARRAYINIT_Private_Constants { REGIONS_EXCEPT_VITAL = 0x7FF, - LOOP_COUNTER = 0x0000000000042FFF, + LOOP_COUNTER = 0x00000000000012B8, // Parallel mode must be set! SELECT_SRAM = 0x1, SELECT_EDRAM = 0x0, START_ABIST_MATCH_VALUE = 0x0000000F00000000 @@ -70,6 +74,11 @@ p9_hcd_core_arrayinit( FAPI_INF(">>p9_hcd_core_arrayinit"); fapi2::buffer<uint64_t> l_data64; + // To get proc DD level + uint8_t l_parallel_abist_nimbus_dd1_workaround = 0; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + #if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT) fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>(); @@ -80,6 +89,17 @@ p9_hcd_core_arrayinit( #ifndef P9_HCD_STOP_SKIP_ARRAYINIT + // Only set ABIST engine to parallel mode for DD1 level + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NDD1_ABIST_PARALLEL, l_chip, + l_parallel_abist_nimbus_dd1_workaround)); + + if (l_parallel_abist_nimbus_dd1_workaround != 0) + { + FAPI_DBG("Scan ec_abst ring"); + FAPI_TRY(fapi2::putRing(i_target, ec_abst), + "Error from putRing (ec_abst)"); + } + FAPI_DBG("Arrayinit all regions except vital"); FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv, REGIONS_EXCEPT_VITAL, |
