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author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2017-03-16 10:14:37 +0100 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-29 02:40:34 -0400 |
commit | ac2848b4918cf5b27a1f9647ee6fd19c8016ffea (patch) | |
tree | 358f3bb3411333a3cdf69e58173d890c356ab896 /src/import | |
parent | ef5c179afb3f587afab105274bf5ba59afc0813d (diff) | |
download | talos-sbe-ac2848b4918cf5b27a1f9647ee6fd19c8016ffea.tar.gz talos-sbe-ac2848b4918cf5b27a1f9647ee6fd19c8016ffea.zip |
p9_sbe_chiplet_reset,p9_sbe_arrayinit
* assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1
in cumulus chip MC chiplet
* Cumulus only dropping MC chiplet
fence during arrayinit
Change-Id: Id339b8707cb2caac62068bdea1c93465b43721e2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38028
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38030
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
5 files changed, 120 insertions, 5 deletions
diff --git a/src/import/chips/p9/common/include/p9_const_common.H b/src/import/chips/p9/common/include/p9_const_common.H index 757294af..51e273c1 100644 --- a/src/import/chips/p9/common/include/p9_const_common.H +++ b/src/import/chips/p9/common/include/p9_const_common.H @@ -78,11 +78,24 @@ struct has_fixfld static const uint8_t value = 255; }; +const uint32_t N0_CHIPLET_ID = 2; +const uint32_t N1_CHIPLET_ID = 3; +const uint32_t N2_CHIPLET_ID = 4; +const uint32_t N3_CHIPLET_ID = 5; +const uint32_t XB_CHIPLET_ID = 6; +const uint32_t MC01_CHIPLET_ID = 7; +const uint32_t MC23_CHIPLET_ID = 8; const uint32_t OB0_CHIPLET_ID = 9; const uint32_t OB1_CHIPLET_ID = 10; const uint32_t OB2_CHIPLET_ID = 11; const uint32_t OB3_CHIPLET_ID = 12; - +const uint32_t PCI0_CHIPLET_ID = 13; +const uint32_t PCI1_CHIPLET_ID = 14; +const uint32_t PCI2_CHIPLET_ID = 15; +const uint32_t EC0_CHIPLET_ID = 0x20; +const uint32_t EC23_CHIPLET_ID = 0x37; +const uint32_t EQ0_CHIPLET_ID = 0x10; +const uint32_t EQ5_CHIPLET_ID = 0x15; #define FIXREG8(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint8_t,unit,meth,expr> { static const uint8_t value = newexpr; }; #define FIXREG32(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint32_t,unit,meth,expr> { static const uint32_t value = newexpr; }; #define FIXREG64(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint64_t,unit,meth,expr> { static const uint64_t value = newexpr; }; diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C index 63385c0e..fd2e1edf 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,7 +58,8 @@ enum P9_SBE_ARRAYINIT_Private_Constants static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, - const fapi2::buffer<uint16_t> i_regions); + const fapi2::buffer<uint16_t> i_regions, + fapi2::buffer<uint8_t> ec_attr_for_cumulus_mc_cplt); static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, @@ -68,8 +69,12 @@ fapi2::ReturnCode p9_sbe_arrayinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_read_attr; FAPI_INF("p9_sbe_arrayinit: Entering ..."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW406337, + i_target_chip, l_read_attr)); + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | @@ -86,7 +91,7 @@ fapi2::ReturnCode p9_sbe_arrayinit(const FAPI_DBG("Call proc_sbe_arryinit_scan0_and_arrayinit_module_function"); FAPI_TRY(p9_sbe_arrayinit_scan0_and_arrayinit_module_function(l_chplt_trgt, - l_regions)); + l_regions, l_read_attr)); FAPI_DBG("clear sdis_n"); FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, false)); @@ -108,12 +113,15 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if success, else error code. static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, - const fapi2::buffer<uint16_t> i_regions) + const fapi2::buffer<uint16_t> i_regions, + fapi2::buffer<uint8_t> ec_attr_for_cumulus_mc_cplt) { bool l_read_reg = false; fapi2::buffer<uint64_t> l_data64; FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Entering ..."); + uint32_t l_chipletID = i_target_chiplet.getChipletNumber(); + FAPI_DBG("Check for chiplet enable"); //Getting NET_CTRL0 register value FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); @@ -122,10 +130,26 @@ static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( if ( l_read_reg ) { + if ( ec_attr_for_cumulus_mc_cplt && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID )) + { + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_DBG("Dropping chiplet fence for MC chiplet in Cumulus"); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + FAPI_DBG("run array_init module for all chiplet except TP, EC, EP"); FAPI_TRY(p9_perv_sbe_cmn_array_init_module(i_target_chiplet, i_regions, LOOP_COUNTER, SELECT_SRAM, SELECT_EDRAM, START_ABIST_MATCH_VALUE)); + if ( ec_attr_for_cumulus_mc_cplt && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID ) ) + { + l_data64.flush<0>(); + l_data64.setBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_DBG("Raising back chiplet fence for MC chiplet in Cummulus chip"); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64)); + } + FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR TIME REPR all chiplets except TP, EC, EP"); FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, i_regions, SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 4bef7660..39286a8d 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -120,6 +120,8 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( static fapi2::ReturnCode p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup( const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); +static fapi2::ReturnCode p9_sbe_chiplet_reset_assert_scan_clk( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); fapi2::ReturnCode p9_sbe_chiplet_reset(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) @@ -449,10 +451,23 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const } } + FAPI_DBG("reading ec_level attr HW404176_ASSERT_SCAN_CLK"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK, + i_target_chip, l_read_attr)); + // Perv without Core/Cache for (auto& targ : l_perv_func_WO_Core_Cache) { + FAPI_TRY(p9_sbe_chiplet_reset_scan0_call(targ)); + + uint32_t l_chipletID = targ.getChipletNumber(); + + if((l_read_attr) && (l_chipletID >= 7 && l_chipletID <= 8)) // cumulus chip & MC chiplet + { + FAPI_DBG("assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_assert_scan_clk(targ)); + } } #ifndef __PPE__ @@ -467,6 +482,28 @@ fapi_try_exit: } + +/// @brief assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_assert_scan_clk( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + FAPI_INF("p9_sbe_chiplet_reset_assert_scan_clk: Entering ..."); + fapi2::buffer<uint64_t> l_data64; + + FAPI_DBG("assert SCAN_CLK_USE_EVEN=1 in OPCG_REG1 for cumulus chip Mc chiplet"); + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_REG1, l_data64)); + l_data64.setBit<PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_REG1, l_data64)); + + + FAPI_INF("p9_sbe_chiplet_reset_assert_scan_clk: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; +} /// @brief Setting up hang pulse counter for all parital good chiplet except for Tp /// /// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 3d9b330c..de294563 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2685,6 +2685,39 @@ </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Only MC in Cumulus need to generate scan clock in even cycle instead of odd + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW406337</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Cumulus only dropping MC chiplet fence during arrayinit + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <!-- End Memory Section --> <!-- ******************************************************************** --> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index cb0eb8f2..c49e3bed 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -373,6 +373,14 @@ attribute tank <name>ATTR_CHIP_EC_FEATURE_NDD1_ABIST_PARALLEL</name> <virtual/> </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</name> + <virtual/> + </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_HW406337</name> + <virtual/> + </entry> <entry> <name>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</name> |