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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2018-09-01 09:09:55 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-09-05 22:36:55 -0500 |
| commit | ab21d9215c0ecf9b018470a63700d32e102501d3 (patch) | |
| tree | 559b180e4a8ec17b86d2569f91929c909246ec42 /src/import | |
| parent | 2bd351fbbd3969f2b2e5ab3a9f97046fba49e456 (diff) | |
| download | talos-sbe-ab21d9215c0ecf9b018470a63700d32e102501d3.tar.gz talos-sbe-ab21d9215c0ecf9b018470a63700d32e102501d3.zip | |
Secure Boot: Whitelist PPE External Interface XCR and SMP lane related register
Whitelists the PPE External Interface XCR register to allow FSP to start/stop
the IO PPE at different phases of system SMP link training to enable
better handling of an A-bus cable pull
Also whitelist registers used in rx_lane_ana_pdwn, rx_lan_dig_pdwn,
rx_tx_lane_pdwn, & rx_lane_disabled HWP
Change-Id: I3f0494064919e5182ef3aba0149a9eb49dd05868
CQ: SW441542
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65603
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65604
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/security/p9_security_white_black_list.csv | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/import/chips/p9/security/p9_security_white_black_list.csv b/src/import/chips/p9/security/p9_security_white_black_list.csv index 27d8767b..b97710cc 100644 --- a/src/import/chips/p9/security/p9_security_white_black_list.csv +++ b/src/import/chips/p9/security/p9_security_white_black_list.csv @@ -207,6 +207,8 @@ Version,Chiplet,Base Address,Chiplet Id - range,Bit Mask,User,Register Name,Desc ,OBUS,0000000009010810,0x09-0x0C,,HWSV,PowerBus OLL TX0 Lane Control register,,write_whitelist, ,OBUS,0000000009010811,0x09-0x0C,,HWSV,PowerBus OLL TX1 Lane Control register,,write_whitelist, ,OBUS,000000000901081A,0x09-0x0C,,HWSV,PowerBus OLL Retrain Threshold register,,write_whitelist, +,OBUS,0000000009011050,0x09-0x0C,,HWSV,PPE External Interface XCR register,,write_whitelist, +,OBUS,8000080009010C3F,0x09-0x0C,,HWSV,rx(tx)_lane_ana_pdwn rx_lane_dig_pdwn and rx_lane_disabled,,write_whitelist, ,Core,0000000020010A9C,0x20-0x37,,HB,Direct injects into logic - no latches!!,,write_whitelist, ,Core,0000000020010A9D,0x20-0x37,,HB,RAS Mode Register,,write_whitelist, ,XBUS,8000000006010C3F,0x06,,HB,,,write_whitelist, |
