Interrupts must be blocked the entire time the thread is stopped.

- Instead of just blocking interrupts during the actual step operation,
  we should have blocked the entire time the thread is stopped.

Change-Id: Ie3006a8882ad996ef62290aeae7103286211ef1f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30186
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30189
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

2 files changed, 44 insertions, 32 deletions

diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C
index 742244d5..ed817cd7 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C
@@ -427,6 +427,20 @@ fapi2::ReturnCode p9_thread_control_sreset(
     FAPI_DBG("p9_thread_control_sreset : Initiating sreset command to core PC logic for threads 0x%x",
              i_threads);
     // No Precondition for Sreset; power management is handled by platform
+    // Clear blocking interrupts
+    {
+        fapi2::buffer<uint64_t> l_mode_data;
+
+        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
+                 i_threads);
+
+        l_mode_data.clearBit<RAS_MODE_MR_FENCE_INTERRUPTS>();
+        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
+                 i_threads);
+    }
+
     // Setup & Initiate SReset Command
     {
         fapi2::buffer<uint64_t> l_scom_data(
@@ -495,6 +509,20 @@ fapi2::ReturnCode p9_thread_control_start(
                         i_threads);
     }
 
+    // Clear blocking interrupts
+    {
+        fapi2::buffer<uint64_t> l_mode_data;
+
+        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
+                 i_threads);
+
+        l_mode_data.clearBit<RAS_MODE_MR_FENCE_INTERRUPTS>();
+        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
+                 i_threads);
+    }
+
     // Start the threads
     {
         fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_START);
@@ -564,6 +592,19 @@ fapi2::ReturnCode p9_thread_control_stop(
                         "p9_thread_control_stop: ERROR: Threads cannot be stopped because they aren't running (threads=%x).", i_threads);
     }
 
+    // Block interrupts while stopped
+    {
+        fapi2::buffer<uint64_t> l_mode_data;
+        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
+                 i_threads);
+
+        l_mode_data.setBit<RAS_MODE_MR_FENCE_INTERRUPTS>();
+        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
+                 i_threads);
+    }
+
     // Stop the threads
     {
         fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_STOP);
@@ -633,21 +674,8 @@ fapi2::ReturnCode p9_thread_control_step(
 
     // Setup single step mode and issue step.
     {
-        fapi2::buffer<uint64_t> l_mode_data;
         fapi2::buffer<uint64_t> l_step_data(g_control_reg_map[i_threads] >> CORE_STEP);
 
-        // Set single step mode.
-        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
-                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
-                 i_threads);
-
-        // i_threads is right aligned
-        l_mode_data |=
-            fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads);
-        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
-                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
-                 i_threads);
-
         // Set issue the step
         FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_step_data),
                  "p9_thread_control_step: putScom error when issuing step command for threads 0x%x",
@@ -682,22 +710,6 @@ fapi2::ReturnCode p9_thread_control_step(
     }
 
 
-    // Reset single step mode
-    {
-        fapi2::buffer<uint64_t> l_mode_data;
-
-        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
-                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
-                 i_threads);
-
-        // i_threads is right aligned
-        l_mode_data &= ~
-                       (fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads));
-        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
-                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
-                 i_threads);
-    }
-
 fapi_try_exit:
     return fapi2::current_err;
 }
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H
index 6c39f07e..7a2f20e4 100755
--- a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H
+++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H
@@ -30,7 +30,7 @@
 // *!               Also used to query the state of a thread.
 //------------------------------------------------------------------------------
 
-// *HWP HWP Owner: Nick Klazynski <dyem@us.ibm.com>
+// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
 // *HWP FW Owner:  Thi Tran <thi@us.ibm.com>
 // *HWP Team:  Quad
 // *HWP Level: 2
@@ -105,8 +105,8 @@ extern "C"
 
     enum PTC_Constants
     {
-        RAS_MODE_STEP_SHIFT       = 52,
-        PTC_STEP_COMP_POLL_LIMIT  = 10,
+        RAS_MODE_MR_FENCE_INTERRUPTS = 57,
+        PTC_STEP_COMP_POLL_LIMIT     = 10,
     };
 
 // Bit positions in the DIRECT_CONTROL register