diff options
| author | Thi Tran <thi@us.ibm.com> | 2017-03-22 11:10:52 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-23 10:03:49 -0400 |
| commit | 7607f6473108cfa30174e5ef5790e395a17c5d1d (patch) | |
| tree | 2ca9d83620dba1c6a8dff7ebb16663036192cd83 /src/import | |
| parent | 4239927ee5de613ba2127f2788b482ab7de0145c (diff) | |
| download | talos-sbe-7607f6473108cfa30174e5ef5790e395a17c5d1d.tar.gz talos-sbe-7607f6473108cfa30174e5ef5790e395a17c5d1d.zip | |
Attribute support of customization of Nimbus DD1 PCI reference clock speed.
Change-Id: I5bb1646868fca15aca744b311ab5d2bc5dd64739
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38297
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38305
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
4 files changed, 30 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 9b8cddd4..4bef7660 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -845,12 +845,14 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie( FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ..."); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, - l_attr_unit_pos)); + l_attr_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); // leverage SS filter PLL to feed PCI PLLs, instead of IO filter PLL - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE, i_target_chiplet.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(), - l_use_ss_pll)); + l_use_ss_pll), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE)"); if ( l_attr_unit_pos != 0x0E ) { diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 3f04745a..3d9b330c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1844,10 +1844,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id> + <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: leverage SS PLL to provide reduced frequency reference clock + DD1 only: enable use of SS PLL to provide reduced frequency reference clock (94 MHz, instead of nominal 100 MHz) for PCI PLL </description> <chipEcFeature> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 71f32599..7328a520 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -136,6 +136,24 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_DD1_SLOW_PCI_REF_CLOCK</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + MRW control to permit Normal (100 MHz) or Slow (94 MHz) operation + of PCIE reference clock. On Nimbus DD1 HW, Slow operation is required + to achieve Gen4 operation. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + NORMAL = 0x00, + SLOW = 0x01 + </enum> + <platInit/> + <writeable/> + </attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 0cfe4c8e..cb0eb8f2 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -354,10 +354,14 @@ attribute tank <virtual/> </entry> <entry> - <name>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</name> + <name>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE</name> <virtual/> </entry> <entry> + <name>ATTR_DD1_SLOW_PCI_REF_CLOCK</name> + <value>0x01</value> + </entry> + <entry> <name>ATTR_CHIP_EC_FEATURE_HW401184</name> <virtual/> </entry> |
