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author | Abhishek Agarwal <abagarw8@in.ibm.com> | 2016-10-04 14:21:43 +0200 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-10-21 11:18:00 -0400 |
commit | 75b59547096745630fe3e27b0c37036f9efeb395 (patch) | |
tree | 439722450b548ec263eafc906698c18760e4b365 /src/import | |
parent | 5871dd0fb8b2114dcd51174692e3ea906c4d76cd (diff) | |
download | talos-sbe-75b59547096745630fe3e27b0c37036f9efeb395.tar.gz talos-sbe-75b59547096745630fe3e27b0c37036f9efeb395.zip |
p9_sbe_scominit update for Async MC
Change-Id: I05e9a81ae0afb9261da4a7835ffe281b68f31b0d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30668
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30671
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
3 files changed, 158 insertions, 127 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index 2b054024..20b76982 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -49,6 +49,7 @@ #include <p9_misc_scom_addresses.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> +#include <p9_sbe_common.H> //------------------------------------------------------------------------------ @@ -80,85 +81,6 @@ const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL; const uint64_t PBA_FIR_ACTION1 = 0x0C0100600C000000ULL; const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL; -// chiplet pervasive FIR constants -const uint64_t PERV_LFIR_ACTION0[15] = -{ - 0x0000000000000000ULL, // TP - 0x0000000000000000ULL, // N0 - 0x0000000000000000ULL, // N1 - 0x0000000000000000ULL, // N2 - 0x0000000000000000ULL, // N3 - 0x0000000000000000ULL, // X - 0x0000000000000000ULL, // MC0 - 0x0000000000000000ULL, // MC1 - 0x0000000000000000ULL, // OB0 - 0x0000000000000000ULL, // OB1 - 0x0000000000000000ULL, // OB2 - 0x0000000000000000ULL, // OB3 - 0x0000000000000000ULL, // PCI0 - 0x0000000000000000ULL, // PCI1 - 0x0000000000000000ULL // PCI2 -}; - -const uint64_t PERV_LFIR_ACTION1[15] = -{ - 0x8000000000000000ULL, // TP - 0x8000000000000000ULL, // N0 - 0x8000000000000000ULL, // N1 - 0x8000000000000000ULL, // N2 - 0x8000000000000000ULL, // N3 - 0x8000000000000000ULL, // X - 0x8000000000000000ULL, // MC0 - 0x8000000000000000ULL, // MC1 - 0x8000000000000000ULL, // OB0 - 0x8000000000000000ULL, // OB1 - 0x8000000000000000ULL, // OB2 - 0x8000000000000000ULL, // OB3 - 0x8000000000000000ULL, // PCI0 - 0x8000000000000000ULL, // PCI1 - 0x8000000000000000ULL // PCI2 -}; - -const uint64_t PERV_LFIR_MASK[15] = -{ - 0xFFFFFFFFFFC00000ULL, // TP - 0xFFFFFFFFFFC00000ULL, // N0 - 0xFFFFFFFFFFC00000ULL, // N1 - 0xFFFFFFFFFFC00000ULL, // N2 - 0xFFFFFFFFFFC00000ULL, // N3 - 0xFFFFFFFFFFC00000ULL, // X - 0xFFFFFFFFFFC00000ULL, // MC0 - 0xFFFFFFFFFFC00000ULL, // MC1 - 0xFFFFFFFFFFC00000ULL, // OB0 - 0xFFFFFFFFFFC00000ULL, // OB1 - 0xFFFFFFFFFFC00000ULL, // OB2 - 0xFFFFFFFFFFC00000ULL, // OB3 - 0xFFFFFFFFFFC00000ULL, // PCI0 - 0xFFFFFFFFFFC00000ULL, // PCI1 - 0xFFFFFFFFFFC00000ULL // PCI2 -}; - -// chiplet XIR constants -const uint64_t PERV_XFIR_MASK[15] = -{ - 0x9FFFFFE000000000ULL, // TP - 0x2007FFE000000000ULL, // N0 - 0x201FFFE000000000ULL, // N1 - 0x200FFFE000000000ULL, // N2 - 0x000007E000000000ULL, // N3 - 0x210FFFE000000000ULL, // X - 0x20007FE000000000ULL, // MC0 - 0x20007FE000000000ULL, // MC1 - 0x29FFFFE000000000ULL, // OB0 - 0x29FFFFE000000000ULL, // OB1 - 0x29FFFFE000000000ULL, // OB2 - 0x29FFFFE000000000ULL, // OB3 - 0x21FFFFE000000000ULL, // PCI0 - 0x207FFFE000000000ULL, // PCI1 - 0x201FFFE000000000ULL // PCI2 -}; - - //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -173,6 +95,8 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) uint64_t l_base_addr_nm1; uint64_t l_base_addr_m; uint64_t l_base_addr_mmio; + uint8_t l_mc_sync_mode; + fapi2::TargetFilter l_target_filter = fapi2::TARGET_FILTER_NONE ; // set fabric topology information in each pervasive chiplet (outside of EC/EP) { @@ -378,55 +302,26 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // configure chiplet pervasive FIRs / XFIRs { - for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV> - (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP | - fapi2::TARGET_FILTER_ALL_NEST | - fapi2::TARGET_FILTER_XBUS | - fapi2::TARGET_FILTER_ALL_MC | - fapi2::TARGET_FILTER_ALL_OBUS | - fapi2::TARGET_FILTER_ALL_PCI), - fapi2::TARGET_STATE_FUNCTIONAL)) + l_target_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP | + fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target, l_mc_sync_mode), + "Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)"); + + if (l_mc_sync_mode) { - uint8_t l_unit_idx; - fapi2::buffer<uint64_t> l_scom_data; - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_idx), - "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); - l_unit_idx--; - - - // PERV LFIR - FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1); - - // reset pervasive FIR - l_scom_data = 0; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR, l_scom_data), - "Error from putScom (PERV_LOCAL_FIR)"); - - // configure pervasive FIR action/mask - l_scom_data = PERV_LFIR_ACTION0[l_unit_idx]; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION0, l_scom_data), - "Error from putScom (PERV_LOCAL_FIR_ACTION0)"); - - l_scom_data = PERV_LFIR_ACTION1[l_unit_idx]; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION1, l_scom_data), - "Error from putScom (PERV_LOCAL_FIR_ACTION1)"); - - l_scom_data = PERV_LFIR_MASK[l_unit_idx]; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_MASK, l_scom_data), - "Error from putScom (PERV_LOCAL_FIR_MASK)"); - - // XFIR - FAPI_DBG("Configuring chiplet XFIR (chiplet ID: %02X)", l_unit_idx + 1); - // reset XFIR - l_scom_data = 0; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_XFIR, l_scom_data), - "Error from putScom (PERV_XFIR)"); - - // configure XFIR mask - l_scom_data = PERV_XFIR_MASK[l_unit_idx]; - FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_FIR_MASK, l_scom_data), - "Error from putScom (PERV_FIR_MASK"); + l_target_filter = static_cast<fapi2::TargetFilter>(l_target_filter | fapi2::TARGET_FILTER_ALL_MC); + } + + for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>(l_target_filter, + fapi2::TARGET_STATE_FUNCTIONAL)) + { + + FAPI_INF("Call p9_sbe_common_configure_chiplet_FIR"); + FAPI_TRY(p9_sbe_common_configure_chiplet_FIR(l_chplt_target)); } } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index 1860261f..20be1030 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -54,6 +54,84 @@ enum P9_SBE_COMMON_Private_Constants CPLT_OPCG_DONE_DC_POLL_COUNT = 10 // count to wait for chiplet opcg done }; +// chiplet pervasive FIR constants +const uint64_t PERV_LFIR_ACTION0[15] = +{ + 0x0000000000000000ULL, // TP + 0x0000000000000000ULL, // N0 + 0x0000000000000000ULL, // N1 + 0x0000000000000000ULL, // N2 + 0x0000000000000000ULL, // N3 + 0x0000000000000000ULL, // X + 0x0000000000000000ULL, // MC0 + 0x0000000000000000ULL, // MC1 + 0x0000000000000000ULL, // OB0 + 0x0000000000000000ULL, // OB1 + 0x0000000000000000ULL, // OB2 + 0x0000000000000000ULL, // OB3 + 0x0000000000000000ULL, // PCI0 + 0x0000000000000000ULL, // PCI1 + 0x0000000000000000ULL // PCI2 +}; + +const uint64_t PERV_LFIR_ACTION1[15] = +{ + 0x8000000000000000ULL, // TP + 0x8000000000000000ULL, // N0 + 0x8000000000000000ULL, // N1 + 0x8000000000000000ULL, // N2 + 0x8000000000000000ULL, // N3 + 0x8000000000000000ULL, // X + 0x8000000000000000ULL, // MC0 + 0x8000000000000000ULL, // MC1 + 0x8000000000000000ULL, // OB0 + 0x8000000000000000ULL, // OB1 + 0x8000000000000000ULL, // OB2 + 0x8000000000000000ULL, // OB3 + 0x8000000000000000ULL, // PCI0 + 0x8000000000000000ULL, // PCI1 + 0x8000000000000000ULL // PCI2 +}; + +const uint64_t PERV_LFIR_MASK[15] = +{ + 0xFFFFFFFFFFC00000ULL, // TP + 0xFFFFFFFFFFC00000ULL, // N0 + 0xFFFFFFFFFFC00000ULL, // N1 + 0xFFFFFFFFFFC00000ULL, // N2 + 0xFFFFFFFFFFC00000ULL, // N3 + 0xFFFFFFFFFFC00000ULL, // X + 0xFFFFFFFFFFC00000ULL, // MC0 + 0xFFFFFFFFFFC00000ULL, // MC1 + 0xFFFFFFFFFFC00000ULL, // OB0 + 0xFFFFFFFFFFC00000ULL, // OB1 + 0xFFFFFFFFFFC00000ULL, // OB2 + 0xFFFFFFFFFFC00000ULL, // OB3 + 0xFFFFFFFFFFC00000ULL, // PCI0 + 0xFFFFFFFFFFC00000ULL, // PCI1 + 0xFFFFFFFFFFC00000ULL // PCI2 +}; + +// chiplet XIR constants +const uint64_t PERV_XFIR_MASK[15] = +{ + 0x9FFFFFE000000000ULL, // TP + 0x2007FFE000000000ULL, // N0 + 0x201FFFE000000000ULL, // N1 + 0x200FFFE000000000ULL, // N2 + 0x000007E000000000ULL, // N3 + 0x210FFFE000000000ULL, // X + 0x20007FE000000000ULL, // MC0 + 0x20007FE000000000ULL, // MC1 + 0x29FFFFE000000000ULL, // OB0 + 0x29FFFFE000000000ULL, // OB1 + 0x29FFFFE000000000ULL, // OB2 + 0x29FFFFE000000000ULL, // OB3 + 0x21FFFFE000000000ULL, // PCI0 + 0x207FFFE000000000ULL, // PCI1 + 0x201FFFE000000000ULL // PCI2 +}; + /// @brief --For all chiplets exit flush /// --For all chiplets enable alignment /// --For all chiplets disable alignemnt @@ -627,3 +705,58 @@ fapi_try_exit: return fapi2::current_err; } + +/// @brief configure chiplet pervasive FIRs / XFIRs +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_configure_chiplet_FIR( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + uint8_t l_unit_idx; + fapi2::buffer<uint64_t> l_scom_data; + FAPI_INF("p9_sbe_common_configure_chiplet_FIR: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, l_unit_idx), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + l_unit_idx--; + + // PERV LFIR + FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1); + + // reset pervasive FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_LOCAL_FIR, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR)"); + + // configure pervasive FIR action/mask + l_scom_data = PERV_LFIR_ACTION0[l_unit_idx]; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_LOCAL_FIR_ACTION0, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION0)"); + + l_scom_data = PERV_LFIR_ACTION1[l_unit_idx]; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_LOCAL_FIR_ACTION1, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION1)"); + + l_scom_data = PERV_LFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_LOCAL_FIR_MASK, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_MASK)"); + + // XFIR + FAPI_DBG("Configuring chiplet XFIR (chiplet ID: %02X)", l_unit_idx + 1); + // reset XFIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_XFIR, l_scom_data), + "Error from putScom (PERV_XFIR)"); + + // configure XFIR mask + l_scom_data = PERV_XFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_FIR_MASK, l_scom_data), + "Error from putScom (PERV_FIR_MASK"); + + FAPI_INF("p9_sbe_common_configure_chiplet_FIR: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H index c9e0e92e..0b365529 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -84,4 +84,7 @@ fapi2::ReturnCode p9_sbe_common_get_pg_vector(const fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets); +fapi2::ReturnCode p9_sbe_common_configure_chiplet_FIR( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + #endif |