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author | Prasad Bg Ranganath <prasadbgr@in.ibm.com> | 2018-08-28 07:09:48 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-08-31 22:11:58 -0500 |
commit | 2bd351fbbd3969f2b2e5ab3a9f97046fba49e456 (patch) | |
tree | 6e5cb9b3731fbe39a3661b259d622ef720659b34 /src/import | |
parent | bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43 (diff) | |
download | talos-sbe-2bd351fbbd3969f2b2e5ab3a9f97046fba49e456.tar.gz talos-sbe-2bd351fbbd3969f2b2e5ab3a9f97046fba49e456.zip |
PM:Some more cleanups in update_ec_eq procedure for core unit xstop case
- Enabled EX check. even if it's EQ is functional
- one more check of clock power off which is
required for mpipl case.
- had one bug during l2/l3 stop clock which fixes status bit update.
Actually clock was stopped but the status bit was not set
in EQ_CLOCK_STAT register.
Key_Cronus_Test=PM_REGRESS
Change-Id: I7e8dbea00235ade5a692198dde7c2e6758809b9f
CQ:SW443537
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65360
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65364
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
4 files changed, 79 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C index 0a511505..b81ba115 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C @@ -101,6 +101,15 @@ p9_hcd_cache_stopclocks( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_is_mpipl)); + //Check if EQ is powered off; if so, return + FAPI_TRY(fapi2::getScom(i_target, EQ_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + return fapi2::current_err; + } + if(l_is_mpipl) { // PB_PURGE related SCOMs should be added to the beginning of diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C index 3d8a81ed..04d06121 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C @@ -46,6 +46,7 @@ #include <p9_hcd_core_stopclocks.H> #include <p9_hcd_cache_stopclocks.H> #include <p9_eq_clear_atomic_lock.H> +#include <p9_quad_scom_addresses_fld.H> #ifdef __PPE__ #include <p9_sbe_ppe_utils.H> #else @@ -103,6 +104,25 @@ p9_hcd_core_stopclocks( l_attr_chip_unit_pos = (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET) % 4; + //Check if EQ is powered off; if so, return + FAPI_TRY(fapi2::getScom(l_quad, EQ_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + return fapi2::current_err; + } + + //Check if core is powered off; if so, return + FAPI_TRY(fapi2::getScom(i_target, C_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<C_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + return fapi2::current_err; + } + + // ---------------------------- // Prepare to stop core clocks // ---------------------------- diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_query_cache_access_state.C b/src/import/chips/p9/procedures/hwp/pm/p9_query_cache_access_state.C index db59f996..7551e589 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_query_cache_access_state.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_query_cache_access_state.C @@ -50,6 +50,7 @@ // ---------------------------------------------------------------------- #include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> #include <p9_query_cache_access_state.H> @@ -84,6 +85,30 @@ p9_query_cache_access_state( FAPI_INF("> p9_query_cache_access_state..."); + + //Check if EQ is powered off; if so, indicate not + //scomable or scannable + FAPI_TRY(fapi2::getScom(i_target, EQ_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + for (auto cnt = 0; cnt < MAX_L2_PER_QUAD; ++cnt) + { + o_l2_is_scomable[cnt] = 0; + o_l2_is_scannable[cnt] = 0; + } + + for (auto cnt = 0; cnt < MAX_L3_PER_QUAD; ++cnt) + { + o_l3_is_scomable[cnt] = 0; + o_l3_is_scannable[cnt] = 0; + } + + return fapi2::current_err; + } + + //Get the stop state from the SSHRC in the EQPPM //First figure out whether we should use the C_PPM_SSHFSP (if FSP platform) or C_PPM_SSHHYP (if HOST platform) FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EXECUTION_PLATFORM, FAPI_SYSTEM, l_execution_platform), diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_query_core_access_state.C b/src/import/chips/p9/procedures/hwp/pm/p9_query_core_access_state.C index b714fd9a..fe0dd886 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_query_core_access_state.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_query_core_access_state.C @@ -75,6 +75,31 @@ p9_query_core_access_state( FAPI_INF("> p9_query_core_access_state..."); + auto l_eq_target = i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + + //Check if quad/core is powered off; if so, indicate + //not scomable or scannable + FAPI_TRY(fapi2::getScom(l_eq_target, EQ_PPM_PFSNS, l_data64), + "Error reading data from EQ_PPM_PFSNS"); + + if (l_data64.getBit<EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + o_is_scomable = 0; + o_is_scanable = 0; + return fapi2::current_err; + } + + FAPI_TRY(fapi2::getScom(i_target, C_PPM_PFSNS, l_data64), + "Error reading data from C_PPM_PFSNS"); + + if (l_data64.getBit<C_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE>()) + { + o_is_scomable = 0; + o_is_scanable = 0; + return fapi2::current_err; + } + + // Get the stop state from the SSHRC in the CPPM FAPI_TRY(fapi2::getScom(i_target, C_PPM_SSHSRC, l_csshsrc), "Error reading data from CPPM SSHSRC"); |