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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2017-03-08 09:46:00 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-23 08:46:20 -0400 |
| commit | 2b98021d5662fe6d003276d5ae5fd0c8b5e438e9 (patch) | |
| tree | 414a11370bc84df4558f74e881354550c61e5887 /src/import | |
| parent | 3372ecda84828639169900b66fba6040630f099a (diff) | |
| download | talos-sbe-2b98021d5662fe6d003276d5ae5fd0c8b5e438e9.tar.gz talos-sbe-2b98021d5662fe6d003276d5ae5fd0c8b5e438e9.zip | |
p9_sbe_tp_chiplet_init3: Start PLL SL clocks
to enable correct OSCLITE operation
Change-Id: Id08f2edfa0e49a260d021fcbeaaf70195a323ecd
CQ: HW402116
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37663
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: DARREN J. DUFFY <darren@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37667
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C index d57a1bda..2c9b8a8d 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -57,7 +57,9 @@ enum P9_SBE_TP_CHIPLET_INIT3_Private_Constants { START_CMD = 0x1, REGIONS_ALL_EXCEPT_PIB_NET_PLL = 0x4FE, - CLOCK_TYPES = 0x7, + CLOCK_TYPES_ALL = 0x7, + REGIONS_PLL = 0x001, + CLOCK_TYPES_SL = 0x4, HW_NS_DELAY = 100000, // unit is nano seconds SIM_CYCLE_DELAY = 1000, // unit is sim cycles POLL_COUNT = 300, // Observed Number of times CBS read for CBS_INTERNAL_STATE_VECTOR @@ -114,7 +116,15 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const FAPI_DBG("l_regions value: %#018lX", l_regions); FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_regions, - CLOCK_TYPES)); + CLOCK_TYPES_ALL)); + + FAPI_DBG("Start perv PLL region SL clocks"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet, + REGIONS_PLL, l_regions)); + FAPI_DBG("l_regions value: %#018lX", l_regions); + + FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_regions, + CLOCK_TYPES_SL)); FAPI_DBG("Calling clock_test2"); FAPI_TRY(p9_sbe_tp_chiplet_init3_clock_test2(i_target_chip)); |
