Axone only-IPL Procedures update to support SBE changes

Using SBE_AXONE_CONFIG compile flag for Axone specific changes

Change-Id: I3d67c8f9ebba9fc18925ae02d1fff3cca8a9440b
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53714
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53735

4 files changed, 219 insertions, 35 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
index fa2d2a48..f2ae836c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -394,8 +394,18 @@ fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
     fapi2::buffer<uint16_t> l_scan_types;
     fapi2::buffer<uint64_t> l_data64;
     int l_timeout = 0;
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    uint32_t l_chipletID = i_target_chiplets.getChipletNumber();
+    fapi2::buffer<uint8_t>  l_is_axone;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_taget_chip = i_target_chiplets.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+#endif
+
     FAPI_INF("p9_perv_sbe_cmn_scan0_module: Entering ...");
 
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9A_SBE_REGION, l_taget_chip, l_is_axone));
+#endif
+
     i_regions.extractToRight<5, 11>(l_regions);
     i_scan_types.extractToRight<4, 12>(l_scan_types);
 
@@ -406,10 +416,24 @@ fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
     l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>();
     FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64));
 
-    FAPI_DBG("Raise region fences for scanned regions");
     //Setting CPLT_CTRL1 register value
     l_data64.flush<0>();
-    l_data64.setBit<4, 11>();  //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = 0b11111111111
+
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+
+    if ((l_is_axone) && (l_chipletID == PERV_CHIPLET_ID))
+    {
+        FAPI_DBG("Raise region fences for scanned regions only");
+        //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_regions
+        l_data64.insertFromRight<4, 11>(l_regions);
+    }
+    else
+#endif
+    {
+        FAPI_DBG("Raise region fences for all regions");
+        l_data64.setBit<4, 11>();  //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = 0b11111111111
+    }
+
     FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64));
 
     FAPI_DBG("Setup all Clock Domains and Clock Types");
@@ -491,3 +515,60 @@ fapi_try_exit:
     return fapi2::current_err;
 
 }
+
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+/// @brief Switching to PCB2PCB Path via scom
+///
+/// @param[in]     i_target_chip     Reference to TARGET_TYPE_PROC_CHIP
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    FAPI_INF("p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom: Entering ...");
+
+    FAPI_DBG("Reading ROOT_CTRL0_REG");
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+
+    if (!l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>())
+    {
+        FAPI_DBG("Setting PCB RESET bit in  ROOT_CTRL0_REG");
+        l_read_reg.setBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+    }
+
+    if (!l_read_reg.getBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>())
+    {
+        FAPI_DBG("Setting PCB2PCB bit in  ROOT_CTRL0_REG");
+        l_read_reg.setBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+    }
+
+    if (l_read_reg.getBit<PERV_ROOT_CTRL0_PIB2PCB_DC>())
+    {
+        FAPI_DBG("Clearing FSI2PCB bit in  ROOT_CTRL0_REG");
+        l_read_reg.clearBit<PERV_ROOT_CTRL0_PIB2PCB_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+    }
+
+    if (l_read_reg.getBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>())
+    {
+        FAPI_DBG("Clearing PIB2PCB bit in  ROOT_CTRL0_REG");
+        l_read_reg.clearBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+    }
+
+    if (l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>())
+    {
+        FAPI_DBG("Clearing PCB RESET bit in  ROOT_CTRL0_REG");
+        l_read_reg.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
+    }
+
+    FAPI_INF("p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
index 86c12d83..348ca281 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -66,4 +66,9 @@ fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
         const fapi2::buffer<uint16_t> i_regions,
         const fapi2::buffer<uint16_t> i_scan_types);
 
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+fapi2::ReturnCode p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+#endif
+
 #endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
index 0fce1c2c..ade897a3 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -50,6 +50,7 @@
 enum P9_SBE_TP_ARRAYINIT_Private_Constants
 {
     REGIONS_EXCEPT_PIB_NET_PLL = 0x4FE,
+    REGIONS_EXCEPT_PIB_NET_SBE_PLL = 0x4DE,
     SCAN_TYPES = 0xDCF,
     LOOP_COUNTER = 0x0000000000042FFF,
     START_ABIST_MATCH_VALUE = 0x0000000F00000000,
@@ -67,8 +68,16 @@ fapi2::ReturnCode p9_sbe_tp_arrayinit(const
                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     fapi2::buffer<uint16_t> l_regions;
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    fapi2::buffer<uint8_t>  l_is_axone;
+#endif
+
     FAPI_INF("p9_sbe_tp_arrayinit: Entering ...");
 
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9A_SBE_REGION, i_target_chip, l_is_axone));
+#endif
+
     FAPI_DBG("Exclude PIBMEM from TP array init");
     //Setting PIBMEM_REPAIR_REGISTER_0 register value
     //PIB.PIBMEM_REPAIR_REGISTER_0 = 0xC000000000000000
@@ -79,10 +88,23 @@ fapi2::ReturnCode p9_sbe_tp_arrayinit(const
                  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
                          fapi2::TARGET_STATE_FUNCTIONAL)[0], true));
 
-    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
-                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
-                         fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_PLL, l_regions));
-    FAPI_DBG("l_regions value: %#018lX", l_regions);
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+
+    if (l_is_axone)
+    {
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                     i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                             fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_SBE_PLL, l_regions));
+        FAPI_DBG("l_regions value: %#018lX", l_regions);
+    }
+    else
+#endif
+    {
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                     i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                             fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_PLL, l_regions));
+        FAPI_DBG("l_regions value: %#018lX", l_regions);
+    }
 
     FAPI_DBG("Call ARRAY INIT Module for Pervasive Chiplet");
     FAPI_TRY(p9_perv_sbe_cmn_array_init_module(
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
index 0e24508f..115b19c5 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -42,12 +42,16 @@
 #include <p9_perv_scom_addresses_fld.H>
 #include <p9n2_perv_scom_addresses_fld.H>
 #include <p9_perv_sbe_cmn.H>
-
+#include <p9_sbe_common.H>
 
 enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants
 {
+    START_CMD = 0x1,
+    CLOCK_TYPES_ALL = 0x7,
+    REGIONS_PIB_NET = 0x300,
     SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF,
     REGIONS_EXCEPT_VITAL_PIB_NET = 0x4FF, // Regions excluding VITAL, PIB and NET
+    REGIONS_EXCEPT_VITAL_PIB_NET_SBE = 0x4DF, // Regions excluding VITAL, PIB, NET and SBE
     SCAN_TYPES_TIME_GPTR_REPR = 0x230
 };
 
@@ -58,7 +62,18 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
     fapi2::buffer<uint64_t> l_data64;
     fapi2::buffer<uint64_t> l_data64_perv_ctrl0;
     fapi2::buffer<uint64_t> l_data64_root_ctrl0;
+    fapi2::buffer<uint64_t> l_data64_cplt_ctrl1;
+    fapi2::buffer<uint64_t> l_read_reg;
     fapi2::buffer<uint8_t> l_read_attr;
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    fapi2::buffer<uint8_t>  l_is_axone;
+#endif
+    fapi2::buffer<uint64_t> l_clk_regions;
+#ifndef __PPE__
+    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_tpchiplet =
+        i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                fapi2::TARGET_STATE_FUNCTIONAL)[0];
+#endif
     FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ...");
 
     FAPI_DBG("Disable local clock gating VITAL");
@@ -66,6 +81,10 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
                            i_target_chip, l_read_attr));
     FAPI_DBG("l_read_attr is %d", l_read_attr);
 
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9A_SBE_REGION, i_target_chip, l_is_axone));
+#endif
+
     //Getting PERV_CTRL0 register value
     FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
                             l_data64_perv_ctrl0));
@@ -81,24 +100,66 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
                                 l_data64_perv_ctrl0));
     }
 
-    FAPI_DBG("Release PCB Reset");
-    //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
-    l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0));
+#ifndef __PPE__
 
-    FAPI_DBG("Enable PCB auto-reset");
-    l_data64.flush<0>().setBit<PERV_RESET_REG_TIMEOUT_EN>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_RESET_REG, l_data64));
-
-    FAPI_DBG("Set Chiplet Enable");
-    //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
-    l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
-
-    FAPI_DBG("Drop TP Chiplet Fence Enable");
-    //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
-    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>();
-    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
+    if(l_is_axone)
+    {
+        FAPI_DBG("Release PCB Reset");
+        //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+        l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0));
+
+        FAPI_DBG("Set Chiplet Enable");
+        //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+        l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
+
+        FAPI_DBG("Drop TP Chiplet Fence Enable");
+        //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+        l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
+
+        FAPI_DBG("Drop NET and PIB region fence")
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_CPLT_CTRL1, l_data64_cplt_ctrl1));
+        l_data64_cplt_ctrl1.clearBit<PERV_1_CPLT_CTRL1_UNUSED_5B>();
+        l_data64_cplt_ctrl1.clearBit<PERV_1_CPLT_CTRL1_UNUSED_6B>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL1, l_data64_cplt_ctrl1));
+
+        FAPI_DBG("Starting clock for PIB and NET");
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet, REGIONS_PIB_NET, l_clk_regions));
+        FAPI_DBG("l_clk_regions value: %#018lX", l_clk_regions);
+        FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_clk_regions, CLOCK_TYPES_ALL));
+
+        FAPI_DBG("Switching to PCB2PCB path")
+        FAPI_TRY(p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(
+                     i_target_chip));
+
+        //Getting ROOT_CTRL0 register value again as it is changed in above function
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM,
+                                l_data64_root_ctrl0));
+    }
+    else
+#endif
+    {
+        FAPI_DBG("Release PCB Reset");
+        //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+        l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0));
+
+        FAPI_DBG("Enable PCB auto-reset");
+        l_data64.flush<0>().setBit<PERV_RESET_REG_TIMEOUT_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_RESET_REG, l_data64));
+
+        FAPI_DBG("Set Chiplet Enable");
+        //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+        l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
+
+        FAPI_DBG("Drop TP Chiplet Fence Enable");
+        //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+        l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0));
+    }
 
     FAPI_DBG("Drop Global Endpoint reset");
     //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
@@ -110,18 +171,33 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
     l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>();  //PIB.ROOT_CTRL0.OOB_MUX = 0
     FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0));
 
-    FAPI_DBG("Region setup call");
-    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
-                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
-                         fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions));
-    FAPI_DBG("l_regions value : %#018lX", l_regions);
+#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
+
+    if(l_is_axone)
+    {
+
+        FAPI_DBG("Region setup call");
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                     i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                             fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET_SBE, l_regions));
+        FAPI_DBG("l_regions value : %#018lX", l_regions);
+    }
+    else
+#endif
+    {
+        FAPI_DBG("Region setup call");
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                     i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                             fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions));
+        FAPI_DBG("l_regions value : %#018lX", l_regions);
+    }
 
-    FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types GPTR, TIME, REPR");
+    FAPI_DBG("Run scan0 module for region except vital,PIB,NET,SBE(SBE only for axone), scan types GPTR, TIME, REPR");
     FAPI_TRY(p9_perv_sbe_cmn_scan0_module(
                  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
                          fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_TIME_GPTR_REPR));
 
-    FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types except GPTR, TIME, REPR");
+    FAPI_DBG("Run scan0 module for region except vital,PIB,NET,SBE(SBE only for axone), scan types except GPTR, TIME, REPR");
     FAPI_TRY(p9_perv_sbe_cmn_scan0_module(
                  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
                          fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions,