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author | Mark Pizzutillo <Mark.Pizzutillo@ibm.com> | 2019-06-06 12:25:48 -0500 |
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committer | Raja Das <rajadas2@in.ibm.com> | 2019-07-26 00:58:33 -0500 |
commit | 39a198fbe82646b4107e766dd763039d1f982509 (patch) | |
tree | 471855ca258e40505ca0c9aff5fc3bb11f86789d /src/import/chips | |
parent | bfe4eb7de200ac1110d683c1187d31b9fa3d8ffe (diff) | |
download | talos-sbe-39a198fbe82646b4107e766dd763039d1f982509.tar.gz talos-sbe-39a198fbe82646b4107e766dd763039d1f982509.zip |
Fix exp_draminit phy_params
Change-Id: I73f1fafe816c7046cff139b4fa815e203b2f2f45
Original-Change-Id: I624caa1310920daf172d6681e7c760442236070f
git-coreq:hostboot:I624caa1310920daf172d6681e7c760442236070f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78469
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 9605cf64..2baf23cf 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -106,11 +106,11 @@ enum attr_eff_engine_fields TSV_8H_SUPPORT = 6, PSTATES = 7, MRAM_SUPPORT = 8, - HEIGHT_3DS = 9, - SPD_CL_SUPPORTED = 10, + SPD_CL_SUPPORTED = 9, + ADDRESS_MIRROR = 10, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = SPD_CL_SUPPORTED, + ATTR_EFF_DISPATCHER = ADDRESS_MIRROR, }; /// @@ -138,6 +138,7 @@ enum ffdc_codes READ_CRCT_ENDIAN = 0x0005, READ_TRAINING_RESPONSE_STRUCT = 0x0006, + SET_EXP_DRAM_ADDRESS_MIRRORING = 0x1040, SET_BYTE_ENABLES = 0x1041, SET_NIBBLE_ENABLES = 0x1042, SET_TAA_MIN = 0x1043, @@ -147,9 +148,8 @@ enum ffdc_codes SET_VREF_DQ_TRAIN_RANGE = 0x1047, SET_PSTATES = 0x1048, SET_MRAM_SUPPORT = 0x1049, - SET_3DS_HEIGHT = 0x1050, - SET_SPD_CL_SUPPORTED = 0x1051, - SET_SERDES_FREQ = 0x1052, + SET_SPD_CL_SUPPORTED = 0x1050, + SET_SERDES_FREQ = 0x1051, }; /// |