diff options
| author | Louis Stermole <stermole@us.ibm.com> | 2017-06-16 12:11:05 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2019-01-11 03:31:29 -0600 |
| commit | a66ed7d254406e8bcd83085e23a087f9becd230f (patch) | |
| tree | 7f340e345c2275a85ec89677df600102fa3597d6 /src/import/chips | |
| parent | f62eba35005d4c60a55f541481838eb6af48a426 (diff) | |
| download | talos-sbe-a66ed7d254406e8bcd83085e23a087f9becd230f.tar.gz talos-sbe-a66ed7d254406e8bcd83085e23a087f9becd230f.zip | |
Move MSS Rosetta map from lab to f/w library, add API
Change-Id: I85cf0991ed0c12c11abf980015b5e1a79cc2c450
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42116
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70349
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 6cba8453..5f019cb8 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -491,4 +491,29 @@ </callout> </hwpError> + <hwpError> + <rc>RC_MSS_C4_PIN_OUT_OF_RANGE</rc> + <description>Indicates a fail when attempting to get a PHY mapping for an out-of-bounds module C4 pin index</description> + <ffdc>MCA_TARGET</ffdc> + <ffdc>TYPE</ffdc> + <ffdc>INDEX</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_NO_C4_PIN_MAPPING</rc> + <description>Indicates a fail when attempting to get a module C4 pin mapping for a given PHY instance and lane</description> + <ffdc>MCA_TARGET</ffdc> + <ffdc>TYPE</ffdc> + <ffdc>DP</ffdc> + <ffdc>LANE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + </hwpErrors> |
