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author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2017-04-19 09:31:37 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-11 10:12:12 -0400 |
commit | b36bfb2e0f77258355cf2a398d5ef2f9e1a9aff9 (patch) | |
tree | 637487d82e9c5ee07e7bb3480ebde2abf52303f0 /src/import/chips | |
parent | 3da6fe6871348160704ece80e51957dec71b0652 (diff) | |
download | talos-sbe-b36bfb2e0f77258355cf2a398d5ef2f9e1a9aff9.tar.gz talos-sbe-b36bfb2e0f77258355cf2a398d5ef2f9e1a9aff9.zip |
ADU Level 3 code, changed owner to Josh, and added comments
Change-Id: I0284435ec138688cb03c4b2f19405ba483886666
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39428
Reviewed-by: JOSHUA L. HANNAN <jlhannan@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39435
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
8 files changed, 347 insertions, 224 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C index fe148b06..cbcbfdc2 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C @@ -31,7 +31,7 @@ // *HWP HWP Owner Christina Graves clgraves@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: SBE // //-------------------------------------------------------------------------- @@ -67,31 +67,28 @@ extern "C" { // Process input flag p9_ADU_oper_flag l_myAduFlag; l_myAduFlag.getFlag(i_flags); - FAPI_DBG("l_myAduFlag = %lu", l_myAduFlag); - //If autoinc is set and this is not a DMA operation unset autoinc before passing the flags through + //If autoinc is set and this is not a DMA operation unset autoinc before passing the flags through since autoinc is only allowed for DMA operations if (l_myAduFlag.getOperationType() != p9_ADU_oper_flag::DMA_PARTIAL) { l_myAduFlag.setAutoIncrement(false); } - FAPI_DBG("l_myAduFlag = %lu", l_myAduFlag); - + //If we were using autoinc and this is the last granule we need to clear autoinc before the last read/write if( i_lastGranule && l_myAduFlag.getAutoIncrement() ) { - //call this function to clear the altd_auto_inc bit before the last iteration FAPI_TRY(p9_adu_coherent_clear_autoinc(i_target), "Error from p9_adu_coherent_clear_autoinc"); } + //If we are doing a read operation read the data if (i_rnw) { - //read the data FAPI_TRY(p9_adu_coherent_adu_read(i_target, i_firstGranule, i_address, l_myAduFlag, io_data), "Error from p9_adu_coherent_adu_read"); } + //Otherwise this is a write and write the data else { - //write the data FAPI_TRY(p9_adu_coherent_adu_write(i_target, i_firstGranule, i_address, l_myAduFlag, io_data), "Error from p9_adu_coherent_adu_write"); } @@ -99,16 +96,18 @@ extern "C" { //If we are not in fastmode or this is the last granule, we want to check the status if ( (i_lastGranule) || (l_myAduFlag.getFastMode() == false) ) { + //If we are using autoincrement and this is not the last granule we expect the busy bit to still be set if ( (l_myAduFlag.getAutoIncrement()) && !i_lastGranule ) { - // Only expect ADU busy if in AUTOINC AND it's not the last granule l_busyHandling = EXPECTED_BUSY_BIT_SET; } + //Otherwise we expect the busy bit to be cleared else { l_busyHandling = EXPECTED_BUSY_BIT_CLEAR; } + //We only want to do the status check if this is not a ci operation if (l_myAduFlag.getOperationType() != p9_ADU_oper_flag::CACHE_INHIBIT) { FAPI_TRY(p9_adu_coherent_status_check(i_target, l_busyHandling, false, @@ -116,7 +115,7 @@ extern "C" { "Error from p9_adu_coherent_status_check"); } - //If it's the last read/write + //If it's the last read/write cleanup the adu if (i_lastGranule) { FAPI_TRY(p9_adu_coherent_cleanup_adu(i_target), @@ -125,17 +124,30 @@ extern "C" { } fapi_try_exit: - fapi2::ReturnCode saveError = fapi2::current_err; + //If there is an error and we want to cleanup the ADU if ( fapi2::current_err && l_myAduFlag.getOperFailCleanup() ) { + //reset the ADU (void) p9_adu_coherent_utils_reset_adu(i_target); uint32_t num_attempts = l_myAduFlag.getNumLockAttempts(); + //Unlock the ADU (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts); } + //Append the input data to an error if we got an error back +#ifndef __PPE__ + + if (fapi2::current_err) + { + p9_adu_coherent_append_input_data(i_address, i_rnw, i_flags, fapi2::current_err); + } + +#endif + FAPI_DBG("Exiting..."); - return saveError; + //Return the error that we got from up above + return fapi2::current_err; } } // extern "C" diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H index b2ac9083..500c7cb9 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file p9_adu_access.H /// @brief Read coherent state of memory via the ADU (FAPI) /// -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: // ---------------------------------------------------------------------------------- // diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C index 8c421d98..a81693b0 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C @@ -27,10 +27,10 @@ /// @file p9_adu_coherent_utils.C /// @brief ADU alter/display library functions (FAPI) /// -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: SBE // //----------------------------------------------------------------------------------- @@ -41,6 +41,7 @@ #include <p9_adu_coherent_utils.H> #include <p9_misc_scom_addresses.H> #include <p9_fbc_utils.H> +#include <p9_misc_scom_addresses_fld.H> extern "C" { @@ -48,50 +49,12 @@ extern "C" // Constant definitions //--------------------------------------------------------------------------------- - //ADU Delay Constants - //ADU register field/bit definitions // ADU Option Register field/bit definitions - const uint32_t FBC_ALTD_WITH_PRE_QUIESCE = 23; - const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT = 28; // Bits 28:47 - const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS = 20; - - const uint32_t FBC_ALTD_WITH_POST_INIT = 51; const uint32_t FBC_ALTD_HW397129 = 52; - const uint32_t FBC_ALTD_POST_INIT_COUNT_START_BIT = 54; // Bits 54:63 - const uint32_t FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS = 10; - - // ADU Command Register field/bit definitions - const uint32_t ALTD_CMD_START_OP_BIT = 2; - const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3; - const uint32_t ALTD_CMD_RESET_FSM_BIT = 4; - const uint32_t ALTD_CMD_RNW_BIT = 5; - const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6; - const uint32_t ALTD_CMD_LOCK_PICK_BIT = 10; - const uint32_t ALTD_CMD_LOCK_BIT = 11; - const uint32_t ALTD_CMD_LOCK_ID_START_BIT = 12; - const uint32_t ALTD_CMD_LOCK_ID_END_BIT = 15; - const uint32_t ALTD_CMD_SCOPE_START_BIT = 16; - const uint32_t ALTD_CMD_SCOPE_END_BIT = 18; - const uint32_t ALTD_CMD_AUTO_INC_BIT = 19; - const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20; - const uint32_t ALTD_CMD_DROP_PRIORITY_MAX_BIT = 21; - const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22; - const uint32_t ALTD_CMD_PIB_DIRECT_BIT = 23; - const uint32_t ALTD_CMD_WITH_TM_QUIESCE_BIT = 24; - const uint32_t ALTD_CMD_TTYPE_START_BIT = 25; - const uint32_t ALTD_CMD_TTYPE_END_BIT = 31; - const uint32_t ALTD_CMD_TSIZE_START_BIT = 32; - const uint32_t ALTD_CMD_TSIZE_END_BIT = 39; - - const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - - ALTD_CMD_SCOPE_START_BIT) + 1; - const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - - ALTD_CMD_TTYPE_START_BIT) + 1; - const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT - - ALTD_CMD_TSIZE_START_BIT) + 1; + //TType Constant variables const uint32_t ALTD_CMD_TTYPE_CL_DMA_RD = 6; //0b0000110 const uint32_t ALTD_CMD_TTYPE_DMA_PR_WR = 38; //0b0100110 const uint32_t ALTD_CMD_TTYPE_CI_PR_RD = 52; //0b0110100 @@ -130,36 +93,8 @@ extern "C" const uint32_t QUIESCE_SWITCH_WAIT_COUNT = 128; const uint32_t INIT_SWITCH_WAIT_COUNT = 128; - // ADU Status Register field/bit definitions - const uint32_t ALTD_STATUS_BUSY_BIT = 0; - const uint32_t ALTD_STATUS_WAIT_CMD_ARBIT = 1; - const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2; - const uint32_t ALTD_STATUS_DATA_DONE_BIT = 3; - const uint32_t ALTD_STATUS_WAIT_RESP_BIT = 4; - const uint32_t ALTD_STATUS_OVERRUN_ERROR_BIT = 5; - const uint32_t ALTD_STATUS_AUTOINC_ERR_BIT = 6; - const uint32_t ALTD_STATUS_COMMAND_ERR_BIT = 7; - const uint32_t ALTD_STATUS_ADDRESS_ERR_BIT = 8; - const uint32_t ALTD_STATUS_PB_OP_HANG_ERR_BIT = 9; - const uint32_t ALTD_STATUS_PB_DATA_HANG_ERR_BIT = 10; - const uint32_t ALTD_STATUS_PB_UNEXPECT_CRESP_ERR_BIT = 11; - const uint32_t ALTD_STATUS_WAIT_PIB_DIRECT = 16; - const uint32_t ALTD_STATUS_PIB_DIRECT_DONE = 17; - const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18; - const uint32_t ALTD_STATUS_ECC_CE_BIT = 48; - const uint32_t ALTD_STATUS_ECC_UE_BIT = 49; - const uint32_t ALTD_STATUS_ECC_SUE_BIT = 50; - const uint32_t ALTD_STATUS_CRESP_START_BIT = 59; - const uint32_t ALTD_STATUS_CRESP_END_BIT = 63; - - const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT - - ALTD_STATUS_CRESP_START_BIT + 1); - //FORCE ECC Register field/bit definitions - const uint32_t ALTD_DATA_ITAG_BIT = 0; - const uint32_t ALTD_DATA_TX_ECC_START_BIT = 1; const uint32_t ALTD_DATA_TX_ECC_END_BIT = 16; - const uint32_t ALTD_DATA_TX_ECC_OVERWRITE_BIT = 17; const uint32_t ALTD_DATA_ECC_MASK = 0xFFFFull; @@ -187,8 +122,10 @@ extern "C" p9_ADU_oper_flag::Transaction_size_t l_transSize; uint32_t l_actualTransSize; + //Get the transaction size l_transSize = l_myAduFlag.getTransactionSize(); + //Translate the transaction size to the actual size (1, 2, 4, or 8 bytes) if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { l_actualTransSize = 1; @@ -209,13 +146,13 @@ extern "C" //Check the address alignment FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)), fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( - i_address), + i_address).set_FLAGS(i_flags), "Address is not cacheline aligned"); //Make sure the address is within the ADU bounds FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS, fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( - i_address), + i_address).set_FLAGS(i_flags), "Address exceeds supported fabric real address range"); @@ -234,9 +171,11 @@ extern "C" bool fbc_running = false; FAPI_DBG("Start"); - //Make sure the fabric is initialized and running + //Get the state of the fabric FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running), "Error from p9_fbc_utils_get_fbc_state"); + + //Make sure the fabric is initialized and running othewise set an error FAPI_ASSERT(fbc_initialized && fbc_running, fapi2::P9_ADU_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED( fbc_initialized).set_RUNNING( @@ -257,10 +196,12 @@ extern "C" { fapi2::ReturnCode rc; FAPI_DBG("Start"); + //From the address figure out when it is going to no longer be within the ADU bound by //doing the max fbc address minus the address and then divide by 8 to get number of bytes //and by 8 to get number of 8 byte granules that can be sent o_numGranules = ((P9_FBC_UTILS_FBC_MAX_ADDRESS - i_address) / 8) / 8; + FAPI_DBG("Exiting"); return rc; } @@ -283,15 +224,15 @@ extern "C" fapi2::buffer<uint64_t> altd_option_reg_data(0); // Set up quiesce - altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>(); - altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT, - FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS> + altd_option_reg_data.setBit<PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE>(); + altd_option_reg_data.insertFromRight<PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT, + PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN> (QUIESCE_SWITCH_WAIT_COUNT); // Setup Post-command init - altd_option_reg_data.setBit<FBC_ALTD_WITH_POST_INIT>(); - altd_option_reg_data.insertFromRight<FBC_ALTD_POST_INIT_COUNT_START_BIT, - FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS> + altd_option_reg_data.setBit<PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT>(); + altd_option_reg_data.insertFromRight<PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT, + PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN> (INIT_SWITCH_WAIT_COUNT); //If DD2 setup workaround for HW397129 to re-enable fastpath for DD2 @@ -316,6 +257,7 @@ extern "C" const bool i_rnw, const uint32_t i_flags) { + //Print the address and the flag along with start FAPI_DBG("Start Addr 0x%.16llX, Flag 0x%.8X", i_address, i_flags); fapi2::ReturnCode rc; @@ -326,13 +268,7 @@ extern "C" p9_ADU_oper_flag::OperationType_t l_operType; p9_ADU_oper_flag::Transaction_size_t l_transSize; - //this routine assumes the lock is held by the caller, preserve - //this locked state - altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>(); - //Write the address into altd_addr_reg - FAPI_DBG("Write PU_ALTD_ADDR_REG 0x%.16llX, Value 0x%.16llX", - PU_ALTD_ADDR_REG, altd_addr_reg_data); FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_ADDR_REG, altd_addr_reg_data), "Error writing to ALTD_ADDR Register"); @@ -341,6 +277,10 @@ extern "C" l_operType = l_myAduFlag.getOperationType(); l_transSize = l_myAduFlag.getTransactionSize(); + //Now work on getting the altd cmd register set up - go through all the bits and set/clear as needed + //this routine assumes the lock is held by the caller, preserve this locked state + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_LOCKED>(); + // --------------------------------------------- // Setting for DMA and CI operations // --------------------------------------------- @@ -351,22 +291,21 @@ extern "C" // --------------------------------------------- // DMA & CI common settings // --------------------------------------------- - // Write the altd_cmd_reg // Set fbc_altd_rnw if it's a read if (i_rnw) { - altd_cmd_reg_data.setBit<ALTD_CMD_RNW_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_RNW>(); } // Clear fbc_altd_rnw if it's a write else { - altd_cmd_reg_data.clearBit<ALTD_CMD_RNW_BIT>(); + altd_cmd_reg_data.clearBit<PU_ALTD_CMD_REG_FBC_RNW>(); } // If auto-inc set the auto-inc bit if (l_myAduFlag.getAutoIncrement() == true) { - altd_cmd_reg_data.setBit<ALTD_CMD_AUTO_INC_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_AUTO_INC>(); } // --------------------------------------------------- @@ -379,33 +318,33 @@ extern "C" // Set TTYPE if (i_rnw) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_RD); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_CI_PR_RD); } else { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_WR); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_CI_PR_WR); } // Set TSIZE if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_1); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_CI_TSIZE_1); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_2); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_CI_TSIZE_2); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_4); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_CI_TSIZE_4); } else { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_8); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_CI_TSIZE_8); } } @@ -420,40 +359,40 @@ extern "C" // Set the tsize to ALTD_CMD_DMAR_TSIZE if (i_rnw) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CL_DMA_RD); - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAR_TSIZE); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_CL_DMA_RD); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_DMAR_TSIZE); } // If a write set ALTD_CMD_TTYPE_DMA_PR_WR // Set the tsize according to flag setting else { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, - ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_DMA_PR_WR); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, + PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_DMA_PR_WR); //Set scope to group scope - altd_cmd_reg_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_GROUP); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_SCOPE, PU_ALTD_CMD_REG_FBC_SCOPE_LEN>(ALTD_CMD_SCOPE_GROUP); // Set TSIZE if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_1); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_DMAW_TSIZE_1); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_2); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_DMAW_TSIZE_2); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_4); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_DMAW_TSIZE_4); } else { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_8); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_DMAW_TSIZE_8); } } } @@ -472,17 +411,17 @@ extern "C" // --------------------------------------------- // Set the start op bit - altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_START_OP>(); // Set operation scope - altd_cmd_reg_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, - ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_SYSTEM); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_SCOPE, + PU_ALTD_CMD_REG_FBC_SCOPE_LEN>(ALTD_CMD_SCOPE_SYSTEM); // Set DROP_PRIORITY = HIGH - altd_cmd_reg_data.setBit<ALTD_CMD_DROP_PRIORITY_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_DROP_PRIORITY>(); // Set AXTYPE = Address only - altd_cmd_reg_data.setBit<ALTD_CMD_ADDRESS_ONLY_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_AXTYPE>(); // --------------------------------------------------- // PB specific: TTYPE & TSIZE @@ -493,33 +432,33 @@ extern "C" FAPI_DBG("ADU operation type: PB OPERATION"); // Set TTYPE - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, - ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, + PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_PB_OPER); // Set TM_QUIESCE - altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE>(); if (l_operType == p9_ADU_oper_flag::PB_DIS_OPER) { // TSIZE for PB operation is fixed value: 0b00001000 - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_DIS_OPERATION_TSIZE); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_PB_DIS_OPERATION_TSIZE); } else { // Set OVERWRITE_PBINIT - altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT>(); // Set up quiesce - altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>(); - altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT, - FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS> + altd_option_reg_data.setBit<PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE>(); + altd_option_reg_data.insertFromRight<PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT, + PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN> (QUIESCE_SWITCH_WAIT_COUNT); FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_OPTION_REG, altd_option_reg_data), "Error writing to ALTD_OPTION Register"); // TSIZE for PB operation is fixed value: 0b00001011 - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_INIT_OPERATION_TSIZE); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_PB_INIT_OPERATION_TSIZE); } } @@ -531,32 +470,33 @@ extern "C" FAPI_DBG("ADU operation type: PMISC"); // Set TTYPE - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, - ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PMISC_OPER); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TTYPE, + PU_ALTD_CMD_REG_FBC_TTYPE_LEN>(ALTD_CMD_TTYPE_PMISC_OPER); // Set TSIZE if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { // Set TM_QUIESCE - altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE>(); - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_PMISC_TSIZE_1); // Set quiesce and init around a switch operation in option reg FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error"); } else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2); + altd_cmd_reg_data.insertFromRight<PU_ALTD_CMD_REG_FBC_TSIZE, + PU_ALTD_CMD_REG_FBC_TSIZE_LEN>(ALTD_CMD_PMISC_TSIZE_2); } } } - //This sets everything that should be set for the ALTD_CMD_Register + //Print out what we are setting for altd cmd register data FAPI_DBG("CMD reg value 0x%016llX", altd_cmd_reg_data); + //Write altd cmd register with the settings that were set above FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to ALTD_CMD Register"); @@ -595,38 +535,43 @@ extern "C" l_itagMode, l_eccMode, l_overrideEccMode); FAPI_DBG(" AUTOINC 0x%.8X", l_autoIncMode); + //Get the write data that was passed in as a uint8 into a uint64 for (int i = 0; i < 8; i++) { write_data |= ( static_cast<uint64_t>(i_write_data[i]) << (56 - (8 * i)) ); } + //Put the uint64 write data into the buffer fapi2::buffer<uint64_t> altd_data_reg_data(write_data); + //If we are doing something with ecc/itag data if (l_accessForceEccReg == true) { + //Read the FORCE_ECC register FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error reading the FORCE_ECC Register"); - //if we want to write the itag bit set it + //if we want to write the itag bit set that bit if (l_itagMode == true) { eccIndex++; - force_ecc_reg_data.setBit<ALTD_DATA_ITAG_BIT>(); + force_ecc_reg_data.setBit<PU_FORCE_ECC_REG_ALTD_DATA_ITAG>(); } //if we want to write the ecc data get the data if (l_eccMode == true) { - force_ecc_reg_data.insertFromRight < ALTD_DATA_TX_ECC_START_BIT, - (ALTD_DATA_TX_ECC_END_BIT - ALTD_DATA_TX_ECC_START_BIT) + 1 > + force_ecc_reg_data.insertFromRight < PU_FORCE_ECC_REG_ALTD_DATA_TX, + PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN > ((uint64_t)i_write_data[eccIndex]); } - //if we want to overwrite the ecc data + //if we want to overwrite the ecc data set that bit if (l_overrideEccMode == true) { - force_ecc_reg_data.setBit<ALTD_DATA_TX_ECC_OVERWRITE_BIT>(); + force_ecc_reg_data.setBit<PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE>(); } + //Write to the FORCE_ECC register FAPI_TRY(fapi2::putScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error writing to the FORCE_ECC Register"); } @@ -640,7 +585,7 @@ extern "C" //read the altd_cmd_register FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG"); //set the start op bit - altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_START_OP>(); //write the altd_cmd_register FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG"); } @@ -652,17 +597,19 @@ extern "C" for (uint32_t i = 0; i < 100000; i++) { + //Check the busy bit if it's busy exit otherwise check the status FAPI_TRY(p9_adu_coherent_status_check(i_target, EXIT_ON_BUSY, false, l_busyBitStatus), "Error from p9_adu_coherent_status_check"); - //If the data done bit is set (the data transfer is done we can go write the data + //If the data done bit is set (the data transfer is done we are done if (!l_busyBitStatus) { break; } } } + //If it's not a ci operation we just want to delay for a while and then this write is done else { //delay to allow time for the write to progress @@ -708,7 +655,7 @@ extern "C" //read the altd_cmd_register FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG"); //set the start op bit - altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_START_OP>(); //write the altd_cmd_register FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG"); } @@ -720,6 +667,7 @@ extern "C" for (uint32_t i = 0; i < 100000; i++) { + //We want to exit if it's still busy and keep polling on that bit - otherwise actually check the status FAPI_TRY(p9_adu_coherent_status_check(i_target, EXIT_ON_BUSY, false, l_busyBitStatus), "Error from p9_adu_coherent_status_check"); @@ -741,15 +689,18 @@ extern "C" //if we want to include the itag and ecc data collect them before the read if ( l_itagMode || l_eccMode ) { + //Read the FORCE_ECC register FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error reading from the FORCE_ECC Register"); + //If we are reading the itag get that data and put it in the read_data array if (l_itagMode) { eccIndex = 9; - o_read_data[8] = force_ecc_reg_data.getBit<ALTD_DATA_ITAG_BIT>(); + o_read_data[8] = force_ecc_reg_data.getBit<PU_FORCE_ECC_REG_ALTD_DATA_ITAG>(); } + //If we are reading the ecc get that data and put it in the read_data array if (l_eccMode) { o_read_data[eccIndex] = (force_ecc_reg_data >> (63 - ALTD_DATA_TX_ECC_END_BIT)) & ALTD_DATA_ECC_MASK; @@ -760,15 +711,12 @@ extern "C" FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_DATA_REG, altd_data_reg_data), "Error reading from the ALTD_DATA Register"); + //Format the uint64 read data into an uint8 array for (int i = 0; i < 8; i++) { o_read_data[i] = (altd_data_reg_data >> (56 - (i * 8))) & 0xFFull; } - FAPI_DBG("o_read_data[8] = %8X", o_read_data[8]); - //o_read_data[0] = altd_data_reg_data; - FAPI_DBG("altd_data_reg_data = %lu\n", altd_data_reg_data); - fapi_try_exit: FAPI_DBG("Exiting..."); return fapi2::current_err; @@ -781,12 +729,14 @@ extern "C" fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0); + //Get the current value from altd_cmd register so we don't write over anything FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from ALTD_CMD Register"); - //write altd_cmd_reg to set the reset_fsm bit - altd_cmd_reg_data.setBit<ALTD_CMD_RESET_FSM_BIT>(); - altd_cmd_reg_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>(); - altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>(); + //set the reset_fsm, clear_status, and locked bits to do an ADU reset + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_RESET_FSM>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_CLEAR_STATUS>(); + altd_cmd_reg_data.setBit<PU_ALTD_CMD_REG_FBC_LOCKED>(); + //Write the altd_cmd register FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error setting the reset_fsm bit from the ALTD_CMD Register"); @@ -805,9 +755,9 @@ extern "C" fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0); - //write altd_cmd_reg to clear the fbc_locked bit + //write all 0s to altd_cmd_reg to cleanup everything FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), - "Error clearing the fbc_locked bit from the ALTD_CMD Register"); + "Error clearing the ALTD_CMD Register"); fapi_try_exit: FAPI_DBG("Exiting..."); @@ -825,22 +775,26 @@ extern "C" fapi2::buffer<uint64_t> l_statusReg(0x0); bool l_statusError = false; + //Check for a successful status 10 times for (int i = 0; i < 10; i++) { + //Delay to allow the write/read/other command to finish FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_STATUS_HW_NS_DELAY, PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY), "fapiDelay error"); l_statusError = false; - // Check the ALTD_STATUS_REG + + // Read ALTD_STATUS_REG FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_statusReg), "Error reading from ALTD_STATUS Register"); + //print out altd_status_reg FAPI_DBG("PU_ALTD_STATUS_REG reg value 0x%016llX", l_statusReg); // ---- Handle busy options ---- // Get busy bit output - o_busyBitStatus = l_statusReg.getBit<ALTD_STATUS_BUSY_BIT>(); + o_busyBitStatus = l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ALTD_BUSY>(); // Handle busy bit according to specified input if (o_busyBitStatus == true) @@ -850,11 +804,13 @@ extern "C" { goto fapi_try_exit; } + // if the busy bit was set and it was expected to be clear there is a status error else if (i_busyBitHandler == EXPECTED_BUSY_BIT_CLEAR) { l_statusError = true; } } + //If the busy bit was not set and it was expected to be set there is a status error else if (i_busyBitHandler == EXPECTED_BUSY_BIT_SET) { l_statusError = true; @@ -863,7 +819,6 @@ extern "C" // ---- Check for other errors ---- // Check the WAIT_CMD_ARBIT bit and make sure it's 0 // Check the ADDR_DONE bit and make sure it's set - // Check the DATA_DONE bit and make sure it's set // Check the WAIT_RESP bit to make sure it's clear // Check the OVERRUN_ERR to make sure it's clear // Check the AUTOINC_ERR to make sure it's clear @@ -877,25 +832,30 @@ extern "C" // Check the ECC_SUE to make sure it's clear l_statusError = ( l_statusError || - l_statusReg.getBit<ALTD_STATUS_WAIT_CMD_ARBIT>() || - !l_statusReg.getBit<ALTD_STATUS_ADDR_DONE_BIT>() || - l_statusReg.getBit<ALTD_STATUS_WAIT_RESP_BIT>() || - l_statusReg.getBit<ALTD_STATUS_OVERRUN_ERROR_BIT>() || - l_statusReg.getBit<ALTD_STATUS_AUTOINC_ERR_BIT>() || - l_statusReg.getBit<ALTD_STATUS_COMMAND_ERR_BIT>() || - l_statusReg.getBit<ALTD_STATUS_ADDRESS_ERR_BIT>() || - l_statusReg.getBit<ALTD_STATUS_PBINIT_MISSING_BIT>() || - l_statusReg.getBit<ALTD_STATUS_ECC_CE_BIT>() || - l_statusReg.getBit<ALTD_STATUS_ECC_UE_BIT>() || - l_statusReg.getBit<ALTD_STATUS_ECC_SUE_BIT>() + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT>() || + !l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ADDR_DONE>() || //The address potion of the operation is complete + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_WAIT_RESP>() || //Waiting for a clean combined response (CResp) + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR>() + || //New data was written before the previous data was used/read or a read was performed without new data arriving + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR>() + || //AutoInc Error indicates internal address counter rolled over the 0.5M boundary + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR>() + || //New command was issued before previous one finished + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR>() + || //Invalid Address error : PB responded with Address Error CResp + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING>() || //attempt to start a command without pb_init active + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ECC_CE>() || //ECC Correctable error + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ECC_UE>() || //ECC Uncorrectable error + l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ECC_SUE>() //ECC Special Uncorrectable error ); - // If Address only operation, do not check for ALTD_STATUS_DATA_DONE_BIT + // If Address only operation, do not check for PU_ALTD_STATUS_REG_FBC_DATA_DONE otherwise it should be set if ( i_addressOnlyOper == false ) { - l_statusError |= !l_statusReg.getBit<ALTD_STATUS_DATA_DONE_BIT>(); + l_statusError |= !l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_DATA_DONE>(); } + //If there is not a status error, we can break out of checking status 10 times if (!l_statusError) { break; @@ -911,10 +871,22 @@ extern "C" FAPI_ERR("ALTD_STATUS_REG = %016llX", l_statusReg); } - FAPI_ASSERT( (l_statusError == false), fapi2::P9_ADU_STATUS_REG_ERR() - .set_TARGET(i_target) - .set_STATUSREG(l_statusReg), - "Status Register check error"); + if (l_statusReg.getBit<PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR>()) + { + //If there's an error, raise an error + FAPI_ASSERT( (l_statusError == false), fapi2::P9_ADU_STATUS_REG_ERR_ADDR_ERR() + .set_TARGET(i_target) + .set_STATUSREG(l_statusReg), + "Status Register check error"); + } + else + { + //If there's an error, raise an error + FAPI_ASSERT( (l_statusError == false), fapi2::P9_ADU_STATUS_REG_ERR_NO_ADDR_ERR() + .set_TARGET(i_target) + .set_STATUSREG(l_statusReg), + "Status Register check error"); + } fapi_try_exit: FAPI_DBG("Exiting..."); @@ -928,10 +900,14 @@ extern "C" fapi2::buffer<uint64_t> altd_cmd_reg_data; + //Get the value of altd_cmd register so we don't write over it FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from ALTD_CMD Register"); - altd_cmd_reg_data.clearBit<ALTD_CMD_AUTO_INC_BIT>(); + //clear the autoinc bit + altd_cmd_reg_data.clearBit<PU_ALTD_CMD_REG_FBC_AUTO_INC>(); + + //Write to the altd_cmd register with the autoinc bit cleared FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error clearing the auto_inc bit from the ALTD_CMD Register"); @@ -953,7 +929,7 @@ extern "C" uint32_t attempt_count = 1; bool lock_pick_first_time = true; - // validate input parameters + // num_attempts cannot be 0, otherwise throw an error if (i_num_attempts == 0) { FAPI_ERR("Invalid value %d for number of lock manipulation attempts", @@ -961,12 +937,13 @@ extern "C" } // set up data buffer to perform desired lock manipulation operation + // If we are locking set the locked bit, reset_fsm bit, and clear_status bit if (i_lock) { FAPI_DBG("Configuring lock manipulation control data buffer to perform lock acquisition"); - lock_control.setBit(ALTD_CMD_LOCK_BIT); - lock_control.setBit<ALTD_CMD_RESET_FSM_BIT>(); - lock_control.setBit<ALTD_CMD_CLEAR_STATUS_BIT>(); + lock_control.setBit(PU_ALTD_CMD_REG_FBC_LOCKED); + lock_control.setBit<PU_ALTD_CMD_REG_FBC_RESET_FSM>(); + lock_control.setBit<PU_ALTD_CMD_REG_FBC_CLEAR_STATUS>(); } else { @@ -1002,15 +979,17 @@ extern "C" //if out of attempts but lock pick is desired try to pick the lock once and see if it works if (i_lock_pick && i_lock && lock_pick_first_time) { - lock_control.setBit(ALTD_CMD_LOCK_PICK_BIT); + lock_control.setBit(PU_ALTD_CMD_REG_FBC_LOCK_PICK); attempt_count--; lock_pick_first_time = false; FAPI_DBG("Trying to do a lock pick as desired"); } + //If we are out of attempts and are not trying to pick the lock or if we already picked the lock, error out else { - FAPI_ERR("Desired ADU lock manipulation was not successful after %d attempts", - i_num_attempts); + FAPI_ASSERT(false, fapi2::P9_ADU_COHERENT_UTILS_LOCK_ERR().set_TARGET(i_target).set_LOCK_PICK(i_lock_pick).set_LOCK( + i_lock).set_NUM_ATTEMPTS(i_num_attempts), + "Ran out of lock attempts or were unable to pick lock"); break; } } @@ -1045,4 +1024,34 @@ extern "C" } + void p9_adu_coherent_append_input_data(const uint64_t i_address, const bool i_rnw, const uint32_t i_flags, + fapi2::ReturnCode& o_rc) + { + +#ifndef __PPE__ + uint64_t l_address = i_address; + bool l_rnw = i_rnw; + uint32_t l_flags = i_flags; + fapi2::ffdc_t ADDRESS; + fapi2::ffdc_t RNW; + fapi2::ffdc_t FLAGS; + ADDRESS.ptr() = static_cast<void*>(&l_address); + ADDRESS.size() = sizeof(l_address); + RNW.ptr() = static_cast<void*>(&l_rnw); + RNW.size() = sizeof(l_rnw); + FLAGS.ptr() = static_cast<void*>(&l_flags); + FLAGS.size() = sizeof(l_flags); + + if ((o_rc == (fapi2::ReturnCode) fapi2::RC_P9_ADU_COHERENT_UTILS_INVALID_ARGS) + || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_ADU_FBC_NOT_INITIALIZED_ERR) + || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_ADU_STATUS_REG_ERR_ADDR_ERR) + || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_ADU_STATUS_REG_ERR_NO_ADDR_ERR) + || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_ADU_COHERENT_UTILS_LOCK_ERR)) + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_P9_ADU_COHERENT_UTILS_EXTRA_INPUT_DATA); + } + +#endif + } + } // extern "C diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H index c59bb17c..48deb8ae 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H @@ -27,10 +27,10 @@ /// @file p9_adu_coherent_utils.H /// @brief Common Code to support ADU get/putmem procedures (FAPI) /// -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: // --------------------------------------------------------------------------------- // *! ADDITIONAL COMMENTS : @@ -79,14 +79,14 @@ extern"C" // Type of ADU operations enum OperationType_t { - CACHE_INHIBIT = 0, - DMA_PARTIAL = 1, + CACHE_INHIBIT = 0, //cache-inhibited 1, 2, 4, or 8 byte read/write + DMA_PARTIAL = 1, //partial cache line direct memory access - always 8 byte read/write PB_DIS_OPER = 2, PMISC_OPER = 3, PB_INIT_OPER = 4 }; - // Transaction size + // Transaction size -- only checked if not DMA enum Transaction_size_t { TSIZE_1 = 1, @@ -648,6 +648,14 @@ extern"C" const bool i_lock, const uint32_t i_num_attempts); +///@brief appends input data to the fapi2 return code if we got an error back +///@param[in] i_address => address for the read or write +///@param[in] i_rnw => whether the operation is a read or write +///@param[in] i_flags => flags that contain information that the PBA needs to know to set up registers +///@param[inout] o_rc => fapi error code to be appended with input data + void p9_adu_coherent_append_input_data(const uint64_t i_address, const bool i_rnw, const uint32_t i_flags, + fapi2::ReturnCode& o_rc); + } // extern "C" #endif //_P9_ADU_COHERENT_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H index 7290d7fe..e680c084 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H @@ -25,10 +25,10 @@ /// @file p9_adu_constants.H /// @brief Constant enums to support ADU get/putmem procedures (FAPI) /// -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWp Consumed by: SBE #ifndef _P9_ADU_CONSTANTS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C index d0bb7f8a..3f2181b9 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C @@ -27,10 +27,10 @@ /// @file p9_adu_setup.C /// @brief Setup the registers for a read/write to the ADU // -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 2 +// *HWP Level: 3 // *HWP Consumed by: SBE // //-------------------------------------------------------------------------- @@ -111,7 +111,6 @@ extern "C" "Error from p9_adu_coherent_setup_registers"); fapi_try_exit: - fapi2::ReturnCode saveError = fapi2::current_err; //if an error has occurred, ADU is dirty, and instructed to clean up, //attempt to reset ADU and free lock (propogate rc of original fail) @@ -121,8 +120,18 @@ extern "C" (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts); } + //Append the input data to an error if we got an error back +#ifndef __PPE__ + + if (fapi2::current_err) + { + p9_adu_coherent_append_input_data(i_address, i_rnw, i_flags, fapi2::current_err); + } + +#endif + FAPI_DBG("Exiting..."); - return saveError; + return fapi2::current_err; } } // extern "C" diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H index 93be5415..868de3e8 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,10 +27,10 @@ /// @file p9_adu_setup.H /// @brief Setup the adu to do reads/writes // -// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com // *HWP FW Owner: Thi Tran thi@us.ibm.com // *HWP Team: Nest -// *HWP Level: 1 +// *HWP Level: 3 // *HWP Consumed by: //----------------------------------------------------------------------------------- // *! ADDITIONAL COMMENTS: diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml index 33fbfc40..bae98acb 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -23,50 +23,135 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> + <!-- This has all of the ADU registers that we need to collect for other errors --> + <registerFfdc> + <id>REG_FFDC_ADU_STATUS_REGISTER</id> + <scomRegister>PU_ALTD_STATUS_REG</scomRegister> + <scomRegister>PU_ALTD_CMD_REG</scomRegister> + <scomRegister>PU_ALTD_DATA_REG</scomRegister> + <scomRegister>PU_ALTD_OPTION_REG</scomRegister> + <scomRegister>PU_ALTD_ADDR_REG</scomRegister> + <scomRegister>PU_FORCE_ECC_REG</scomRegister> + </registerFfdc> <!-- ******************************************************************** --> <hwpError> <sbeError/> <rc>RC_P9_ADU_COHERENT_UTILS_INVALID_ARGS</rc> <description> Procedure: p9_adu_coherent_utils - ADU access or setup not attempted, ADU access or setup is stopped + There is an invalid argument (misaligned address or address out of the + fabric address range) being passed to the adu access or adu setup + procedure </description> <ffdc>TARGET</ffdc> <ffdc>ADDRESS</ffdc> + <ffdc>FLAGS</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <sbeError/> - <rc>RC_P9_ADU_COHERENT_UTILS_RESET_ERR</rc> + <rc>RC_P9_ADU_FBC_NOT_INITIALIZED_ERR</rc> <description> Procedure: p9_adu_coherent_utils - ADU Reset had a problem, the ADU was not actually reset + The fabric was not initialized or not running </description> <ffdc>TARGET</ffdc> + <ffdc>INITIALIZED</ffdc> + <ffdc>RUNNING</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <sbeError/> - <rc>RC_P9_ADU_FBC_NOT_INITIALIZED_ERR</rc> + <rc> RC_P9_ADU_STATUS_REG_ERR_NO_ADDR_ERR</rc> <description> Procedure: p9_adu_coherent_utils - The fabric was not initialized or not running + The ALTD_STATUS_REGISTER contains unexpected status with no indication + of a combined response address error </description> <ffdc>TARGET</ffdc> - <ffdc>INITIALIZED</ffdc> - <ffdc>RUNNING</ffdc> + <ffdc>ADDRESS</ffdc> + <ffdc>STATUSREG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_ADU_STATUS_REGISTER</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <target>TARGET</target> + </collectRegisterFfdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> </hwpError> <!-- ******************************************************************** --> <hwpError> <sbeError/> - <rc> RC_P9_ADU_STATUS_REG_ERR</rc> + <rc> RC_P9_ADU_STATUS_REG_ERR_ADDR_ERR</rc> <description> Procedure: p9_adu_coherent_utils - The ALTD_STATUS_REGISTER has something high or low that was not expected + The ALTD_STATUS_REGISTER contains unexpected status with an indication + of a combined response address error </description> <ffdc>TARGET</ffdc> + <ffdc>ADDRESS</ffdc> <ffdc>STATUSREG</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_ADU_STATUS_REGISTER</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <target>TARGET</target> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_P9_ADU_COHERENT_UTILS_LOCK_ERR</rc> + <description> + Procedure:p9_adu_coherent_utils + Number of lock attempts exceeded when attempting to acquire the ADU lock or + error occured when attempting to pick the ADU lock + </description> + <ffdc>TARGET</ffdc> + <ffdc>LOCK_PICK</ffdc> + <ffdc>LOCK</ffdc> + <ffdc>NUM_ATTEMPTS</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_ADU_STATUS_REGISTER</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <target>TARGET</target> + </collectRegisterFfdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> </hwpError> <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_P9_ADU_COHERENT_UTILS_EXTRA_INPUT_DATA</rc> + <description> + Procedure:p9_adu_coherent_utils + Error code used to collect HWP input arguments + </description> + <ffdc>ADDRESS</ffdc> + <ffdc>RNW</ffdc> + <ffdc>FLAGS</ffdc> + </hwpError> </hwpErrors> - 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