diff options
| author | Yue Du <daviddu@us.ibm.com> | 2017-05-18 16:57:33 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-20 02:38:58 -0400 |
| commit | 7a276030571db8fead56e947375bdb8bb47f8e65 (patch) | |
| tree | 464b6c19f192c8e3650311a412265b7a20a7ff25 /src/import/chips | |
| parent | 752076d20988c18fcdf452b1f9f8970cf52cc2c6 (diff) | |
| download | talos-sbe-7a276030571db8fead56e947375bdb8bb47f8e65.tar.gz talos-sbe-7a276030571db8fead56e947375bdb8bb47f8e65.zip | |
Istep4: procedures upgrade to level3
Change-Id: I281a7ba91a13f4694de78d65edb8a9ea65e4756e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40733
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40740
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
61 files changed, 842 insertions, 790 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C index d06e3e86..5f3a9be5 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,12 +31,12 @@ /// Upon completion, scan0 flush all rings /// except Vital, Repair, GPTR, TIME and DPLL -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H index 42eeaa5d..616fce28 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief EX Initialize arrays /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_ARRAYINIT_H__ #define __P9_HCD_CACHE_ARRAYINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C index f31deedf..6220f0c9 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,12 +29,12 @@ /// Procedure Summary: /// Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes @@ -58,30 +58,9 @@ p9_hcd_cache_chiplet_init( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) { FAPI_INF(">>p9_hcd_cache_chiplet_init"); - /* - #ifndef P9_HCD_STOP_SKIP_FLUSH - //-------------------------------------------- - // perform scan0 module for pervasive chiplet - //-------------------------------------------- - // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest - // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has - // all stumps less than 8191, the loop can be removed. - fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = - i_target.getParent<fapi2::TARGET_TYPE_PERV>(); - FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings"); - - for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, - p9hcd::SCAN0_REGION_ALL_BUT_ANEP_DPLL, - p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); - - fapi_try_exit: - - #endif - */ FAPI_INF("<<p9_hcd_cache_chiplet_init"); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H index 82172678..7a85a952 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Cache Flush/Initialize /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__ #define __P9_HCD_CACHE_CHIPLET_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C index bb1715ad..23a9819b 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C @@ -31,8 +31,8 @@ // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> // *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> // *HWP Team : Perv -// *HWP Level : 2 -// *HWP Consumed by : SBE +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 //------------------------------------------------------------------------------ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H index 051db751..4b2f6ff8 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,8 +31,8 @@ // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> // *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> // *HWP Team : Perv -// *HWP Level : 2 -// *HWP Consumed by : SBE +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 //------------------------------------------------------------------------------ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C index 7599c5c9..45deabc9 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -35,12 +35,12 @@ /// - Drop glsmux async reset /// Scan0 flush entire cache chiplet -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -80,11 +80,13 @@ enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS CACHE_GLSMUX_RESET_DELAY_REF_CYCLES = 40 }; -/// @todo RTC162433 DD2 revisit HW388878 -/// This is going to break on Nimbus DD2.0 and Cumulus SoA testing. -/// need more discussion in HW/FW interlock on how to handle this. +// This workaround is disabled on DD2+, the ring length data below is from DD1 enum HW388878_DD1_FIX_CONSTATNS { + CACHE_CLK_START_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CACHE_CLK_START_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CACHE_CLK_START_POLL_DELAY_SIM_CYCLE = 32000, // 320k sim cycle delay + // Eq_fure + Ex_l2_fure(ex0) + Ex_l2_fure(ex1) DD1_EQ_FURE_RING_LENGTH = (46532 + 119192 + 119192) }; @@ -291,6 +293,7 @@ p9_hcd_dd1_vcs_workaround( fapi2::buffer<uint64_t> l_data64; uint64_t l_regions; uint32_t l_timeout; + uint32_t l_poll_loops; uint32_t l_loop; #ifndef __PPE__ @@ -352,23 +355,33 @@ p9_hcd_dd1_vcs_workaround( FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); FAPI_DBG("Poll for perv/l20/l21 clocks running via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP); + l_poll_loops = CACHE_CLK_START_POLL_TIMEOUT_HW_NS / + CACHE_CLK_START_POLL_DELAY_HW_NS; do { + fapi2::delay(CACHE_CLK_START_POLL_DELAY_HW_NS, + CACHE_CLK_START_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + while((l_data64.getBit<8>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_CLK_START_TIMEOUT() + .set_EQ_CPLT_STAT(l_data64) + .set_CACHE_CLK_START_POLL_DELAY_HW_NS(CACHE_CLK_START_POLL_DELAY_HW_NS) + .set_CACHE_CLK_START_POLL_TIMEOUT_HW_NS(CACHE_CLK_START_POLL_TIMEOUT_HW_NS) + .set_CACHE_TARGET(i_target), "perv/l20/l21 Clock Start Timeout"); FAPI_DBG("Check perv/l20/l21 clocks running"); FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_ARY, l_data64)); FAPI_ASSERT(((l_data64 & l_regions) == 0), - fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), + fapi2::CACHE_CLK_START_FAILED() + .set_EQ_CLK_STAT(l_data64) + .set_CACHE_TARGET(i_target), "perv/l20/l21 Clock Start Failed"); FAPI_DBG("perv/l20/l21 clocks running now"); diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H index 5aaf24e9..70854006 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Cache Chiplet Reset /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__ #define __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C index 8ec1d04e..e48d9849 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -33,12 +33,12 @@ /// Historically this was stored in MVPD keywords are #R, #G. Still stored in /// MVPD, but SBE image is customized with rings for booting cores -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H index 20a28f27..24e91f25 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Load DPLL ring for EX non-core /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_DPLL_INITF_H__ #define __P9_HCD_CACHE_DPLL_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C index d6ca2efe..0a23dbdb 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -50,12 +50,12 @@ /// 2) If grid clock connected to dpll clkout, /// bypass also has to be asserted to allow refclk on grid -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes @@ -72,9 +72,13 @@ enum P9_HCD_CACHE_DPLL_SETUP_CONSTANTS { - CACHE_DPLL_LOCK_TIMEOUT_IN_MS = 1, - CACHE_DPLL_CLK_START_TIMEOUT_IN_MS = 1, - CACHE_ANEP_CLK_START_TIMEOUT_IN_MS = 1 + DPLL_LOCK_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + DPLL_LOCK_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + DPLL_LOCK_POLL_DELAY_SIM_CYCLE = 320000, // 320k sim cycle delay + + DPLL_START_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + DPLL_START_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + DPLL_START_POLL_DELAY_SIM_CYCLE = 320000 // 320k sim cycle delay }; //----------------------------------------------------------------------------- @@ -88,7 +92,7 @@ p9_hcd_cache_dpll_setup( FAPI_INF(">>p9_hcd_cache_dpll_setup"); fapi2::buffer<uint64_t> l_data64; uint8_t l_dpll_bypass; - uint32_t l_timeout; + uint32_t l_poll_loops; auto l_parent_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); #ifndef __PPE__ @@ -139,24 +143,33 @@ p9_hcd_cache_dpll_setup( FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); FAPI_DBG("Poll for DPLL clock running via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CACHE_DPLL_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = DPLL_START_POLL_TIMEOUT_HW_NS / + DPLL_START_POLL_DELAY_HW_NS; do { + fapi2::delay(DPLL_START_POLL_DELAY_HW_NS, + DPLL_START_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_DPLLCLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + while((l_data64.getBit<8>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_DPLL_CLK_START_TIMEOUT() + .set_EQ_CPLT_STAT(l_data64) + .set_DPLL_START_POLL_DELAY_HW_NS(DPLL_START_POLL_DELAY_HW_NS) + .set_DPLL_START_POLL_TIMEOUT_HW_NS(DPLL_START_POLL_TIMEOUT_HW_NS) + .set_CACHE_TARGET(i_target), "DPLL Clock Start Timeout"); FAPI_DBG("Check DPLL clock running via CLOCK_STAT_SL[14]"); FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); FAPI_ASSERT((l_data64.getBit<14>() == 0), - fapi2::PMPROC_DPLLCLKSTART_FAILED().set_EQCLKSTAT(l_data64), + fapi2::CACHE_DPLL_CLK_START_FAILED() + .set_EQ_CLK_STAT(l_data64) + .set_CACHE_TARGET(i_target), "DPLL Clock Start Failed"); FAPI_DBG("DPLL clock running now"); @@ -165,11 +178,14 @@ p9_hcd_cache_dpll_setup( if (l_dpll_bypass == 0) { FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CACHE_DPLL_LOCK_TIMEOUT_IN_MS; + l_poll_loops = DPLL_LOCK_POLL_TIMEOUT_HW_NS / + DPLL_LOCK_POLL_DELAY_HW_NS; do { + fapi2::delay(DPLL_LOCK_POLL_DELAY_HW_NS, + DPLL_LOCK_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64)); #ifndef __PPE__ @@ -188,11 +204,14 @@ p9_hcd_cache_dpll_setup( #endif } - while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_DPLL_LOCK_TIMEOUT() - .set_EQQPPMDPLLSTAT(l_data64), + while ((l_data64.getBit<63>() != 1 ) && (--l_poll_loops != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_DPLL_LOCK_TIMEOUT() + .set_EQ_QPPM_DPLL_STAT(l_data64) + .set_DPLL_LOCK_POLL_TIMEOUT_HW_NS(DPLL_LOCK_POLL_TIMEOUT_HW_NS) + .set_DPLL_LOCK_POLL_DELAY_HW_NS(DPLL_LOCK_POLL_DELAY_HW_NS) + .set_CACHE_TARGET(i_target), "DPLL Lock Timeout"); FAPI_DBG("DPLL is locked now"); diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H index 5674c532..1477f295 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Quad DPLL Setup /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_DPLL_SETUP_H__ #define __P9_HCD_CACHE_DPLL_SETUP_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C index a0858bae..bd4918a8 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C @@ -35,12 +35,12 @@ /// Check for the presence of core override TIME ring from image; /// if found, apply; if not, apply core base TIME from image -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H index d42f1927..f712082d 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Load GPTR and Time for EX non-core /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__ #define __P9_HCD_CACHE_GPTR_TIME_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C index 503723bf..1badecfe 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C @@ -36,12 +36,12 @@ /// Note: all caches that are in the Cache Multicast group will be /// initialized to the same values via multicast scans -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -208,8 +208,9 @@ p9_hcd_cache_initf( if(l_data64 != 0xa5a5a5a5a5a5a5a5) { FAPI_ASSERT(false, - fapi2::P9_HCD_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL() - .set_EQ_SCAN64_VAL(l_data64), + fapi2::NDD1_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL() + .set_EQ_SCAN64_VAL(l_data64) + .set_CACHE_TARGET(i_target), "Incorrect Value from EQ_SCAN64, Expected Value [0xa5a5a5a5a5a5a5a5]"); } } diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H index 2931703f..ae977849 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H @@ -27,12 +27,12 @@ /// @brief EX (non-core) scan init /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_INITF_H__ #define __P9_HCD_CACHE_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C index 0b465eb4..9d4da8a5 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C @@ -24,13 +24,7 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_cache_occ_runtime_scom.C -/// @brief EX OCC runtime scoms -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:SGPE -/// *HWP Level : 1 +/// @brief EQ OCC runtime scoms /// /// Procedure Summary: /// Run-time updates from OCC code that are put somewhere revisit with OCC FW team @@ -39,54 +33,37 @@ /// Placeholder at this point /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 + //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include <fapi2.H> -//#include <common_scom_addresses.H> -//will be replaced with real scom address header file + #include "p9_hcd_cache_occ_runtime_scom.H" //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ -#define host_runtime_scom 0 //------------------------------------------------------------------------------ -// Procedure: EX OCC runtime SCOMS +// Procedure: EQ OCC runtime SCOMs //------------------------------------------------------------------------------ -extern "C" +fapi2::ReturnCode +p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) { + FAPI_INF(">>p9_hcd_core_occ_runtime_scom"); - fapi2::ReturnCode - p9_hcd_cache_occ_runtime_scom( - const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) - { - -#if 0 - fapi2::buffer<uint64_t> data; - - // Run the SCOM sequence if the SCOM procedure is defined - // - la A0, occ_runtime_scom - // - ld D0, 0, A0 - // - braz D0, 1f - FAPI_INF("Launching OCC Runtime SCOM routine") - // - bsrd D0 - // - 1: - - return fapi2::FAPI2_RC_SUCCESS; - - FAPI_CLEANUP(); - return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; - -#endif - - return fapi2::FAPI2_RC_SUCCESS; - - } // Procedure + FAPI_INF("<<p9_hcd_core_occ_runtime_scom"); + return fapi2::FAPI2_RC_SUCCESS; +} -} // extern C diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H index 233342f6..973815dc 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,29 +24,29 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_cache_occ_runtime_scom.H -/// @brief EX OCC runtime scoms -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:SGPE -/// *HWP Level : 1 +/// @brief EQ OCC runtime scoms /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 + #ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ #define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ -extern "C" -{ +#include <fapi2.H> /// @typedef p9_hcd_cache_occ_runtime_scom_FP_t /// function pointer typedef definition for HWP call support - typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( - const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); - +typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); -/// @brief EX OCC runtime scoms -/// +extern "C" +{ +/// @brief EQ OCC runtime scoms /// @param [in] i_target TARGET_TYPE_EQ target /// /// @attr @@ -56,8 +56,6 @@ extern "C" fapi2::ReturnCode p9_hcd_cache_occ_runtime_scom( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); - - -} // extern C +} #endif // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C index 7478dd8a..6e688d38 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C @@ -33,12 +33,12 @@ /// Check for valid power on completion /// Polled Timeout: 100us -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H index 4191244a..ffb3c5fa 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Cache Chiplet Power-on /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM -// *HWP Level : 2 // *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_POWERON_H__ #define __P9_HCD_CACHE_POWERON_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C index 19116807..1b10b97e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,13 +24,7 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_cache_ras_runtime_scom.C -/// @brief EX FSP/Host runtime scoms -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SGPE -/// *HWP Level : 1 +/// @brief EQ FSP/Host runtime scoms /// /// Procedure Summary: /// Run-time updates by FSP/Host(including HostServices and Hypervisors) @@ -44,128 +38,37 @@ /// L2/L3 Repairs /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 + //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ -#include <fapi2.H> -//#include <common_scom_addresses.H> -//will be replaced with real scom address header file + #include "p9_hcd_cache_ras_runtime_scom.H" //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ -#define host_runtime_scom 0 //------------------------------------------------------------------------------ -// Procedure: EX FSP/HOST runtime scoms +// Procedure: EQ FSP/HOST runtime scoms //------------------------------------------------------------------------------ -extern "C" +fapi2::ReturnCode +p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) { + FAPI_INF(">>p9_hcd_cache_ras_runtime_scom"); - fapi2::ReturnCode - p9_hcd_cache_ras_runtime_scom( - const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) - { - -#if 0 - fapi2::buffer<uint64_t> data; - - // Run the SCOM sequence if the SCOM procedure is defined - // - la A0, sp_runtime_scom - // - ld D0, 0, A0 - // - braz D0, 1f - //FAPI_INF("Launching SP Runtime SCOM routine") - // - bsrd D0 - // - 1: - // - - // Run the SCOM sequence if the SCOM procedure is defined. - // - la A0, host_runtime_scom - // - ld D1, 0, A0 - // - braz D1, 1f - - // Prep P1 - // - setp1_mcreadand D0 - -#if 0 - // Disable the AISS to allow the override - // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // = andi D0, D0, ~(BIT(1)) - // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 - // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts - // RAMs (SCOMs actually) in the IPL "Nap" state - // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // = ori D0, D0, (BIT(15)) - // = andi D0, D0, ~(BIT(21)) - // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 -#endif - - // Branch to sub_slw_runtime_scom() - FAPI_INF("Launching Host Runtime SCOM routine") - // - bsrd D1 - - // Prep P1 - // - setp1_mcreadand D0 - -#if 0 - // Clear regular wake-up and restore PSCOM fence in OHA - // These were established in p9_sbe_ex_scominit.S - // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // = andi D0, D0, ~(BIT(15)) - // = ori D0, D0, BIT(21) - // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 - // Enable the AISS to allow further operation - // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // = ori D0, D0, (BIT(1)) - // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 -#endif - - // - bra 2f - // - 1: - - // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped - // - setp1_mcreadand D0 - -#if 0 - // Clear regular wake-up and restore PSCOM fence in OHA - // These were established in p9_sbe_ex_scominit.S - // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // = andi D0, D0, ~BIT(1) - // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 - // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // = andi D0, D0, ~(BIT(15)) - // = ori D0, D0, BIT(21) - // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 - // Enable the AISS to allow further operation - // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // = ori D0, D0, (BIT(1)) - // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 -#endif - // - 2: - - // If using cv_multicast, we need to set the magic istep number here - // - la A0, p9_sbe_select_ex_control - // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX - // - braz D0, 3f - FAPI_DBG("Setting istep num to magic number because cv_multicast is set") - // - lpcs P1, MBOX_SBEVITAL_0x0005001C - // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) - // - 3: - - return fapi2::FAPI2_RC_SUCCESS; - - FAPI_CLEANUP(); - return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; - -#endif - - return fapi2::FAPI2_RC_SUCCESS; - - } // Procedure + FAPI_INF("<<p9_hcd_cache_ras_runtime_scom"); + return fapi2::FAPI2_RC_SUCCESS; +} -} // extern C diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H index ccdd3c50..517bd35e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,28 +24,29 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_cache_ras_runtime_scom.H -/// @brief EX FSP/Host runtime scoms -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:SGPE -/// *HWP Level : 1 +/// @brief EQ FSP/Host runtime scoms /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ #define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ -extern "C" -{ +#include <fapi2.H> /// @typedef p9_hcd_cache_ras_runtime_scom_FP_t /// function pointer typedef definition for HWP call support - typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( - const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); +typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); -/// @brief EX FSP/Host runtime scoms +extern "C" +{ +/// @brief EQ FSP/Host runtime scoms /// /// @param [in] i_target TARGET_TYPE_EQ target /// @@ -56,8 +57,6 @@ extern "C" fapi2::ReturnCode p9_hcd_cache_ras_runtime_scom( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); - - -} // extern C +} #endif // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C index eac5ce08..dd0f8a20 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,12 +33,12 @@ /// Historically this was stored in MVPD keywords are #R, #G. Still stored in /// MVPD, but SBE image is customized with rings for booting cores -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H index bc3b1153..67ca2628 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Load Repair ring for EX non-core /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_REPAIR_INITF_H__ #define __P9_HCD_CACHE_REPAIR_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C index d7047ce4..a8574d7f 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C @@ -27,12 +27,12 @@ /// @brief Cache Customization SCOMs /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H index 30e14793..61f1bc45 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H @@ -27,12 +27,12 @@ /// @brief Cache Customization SCOMs /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_SCOMCUST_H__ #define __P9_HCD_CACHE_SCOMCUST_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C index 80b3c643..370a69e9 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C @@ -33,12 +33,12 @@ /// DTS Initialization sequense /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -181,7 +181,9 @@ p9_hcd_cache_scominit( auto l_core_targets = l_ex.getChildren<fapi2::TARGET_TYPE_CORE>(); FAPI_ASSERT((l_core_targets.size() != 0), - fapi2::PMPROC_CACHESCOMINIT_NOGOODCOREINEX().set_QCSR(l_qcsr), + fapi2::CACHE_SCOMINIT_NO_GOOD_CORE_IN_EX() + .set_QCSR(l_qcsr) + .set_CACHE_TARGET(i_target), "NO Good Children Cores under this So-Called Good EX!"); auto l_core = l_core_targets.begin(); diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H index 26029adc..b70a2199 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Cache Customization SCOMs /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_SCOMINIT_H__ #define __P9_HCD_CACHE_SCOMINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index 5d50a6c3..29bbc3a0 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -50,12 +50,12 @@ /// (Done) Check for cache xstop, If so, error /// (Done) Clear flushmode_inh to go into flush mode -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -72,9 +72,18 @@ enum P9_HCD_CACHE_STARTCLOCKS_CONSTANTS { - CACHE_CLK_SYNC_TIMEOUT_IN_MS = 1, - CACHE_CLK_START_TIMEOUT_IN_MS = 1, - CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES = 255 + CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CACHE_CLK_SYNC_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CACHE_CLK_SYNC_POLL_DELAY_SIM_CYCLE = 32000, // 320k sim cycle delay + + CACHE_CPLT_ALIGN_DELAY_CACHE_CYCLES = 255, // in cache cycles + CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CACHE_CPLT_ALIGN_POLL_DELAY_SIM_CYCLE = 32000, // 320k sim cycle delay + + CACHE_CLK_START_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CACHE_CLK_START_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CACHE_CLK_START_POLL_DELAY_SIM_CYCLE = 32000 // 320k sim cycle delay }; //------------------------------------------------------------------------------ @@ -94,7 +103,7 @@ p9_hcd_cache_startclocks( uint64_t l_l2pscom_mask; uint64_t l_l3pscom_mask; uint32_t l_scom_addr; - uint32_t l_timeout; + uint32_t l_poll_loops; uint32_t l_attr_system_id = 0; uint8_t l_attr_group_id = 0; uint8_t l_attr_chip_id = 0; @@ -232,18 +241,25 @@ p9_hcd_cache_startclocks( FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2sync_clock)); FAPI_DBG("Poll for EX-L2 clock sync dones via QPPM_QACSR[36,37]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CACHE_CLK_SYNC_TIMEOUT_IN_MS; + l_poll_loops = CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS / + CACHE_CLK_SYNC_POLL_DELAY_HW_NS; do { + fapi2::delay(CACHE_CLK_SYNC_POLL_DELAY_HW_NS, + CACHE_CLK_SYNC_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64)); } while(((l_data64 & l_l2sync_clock) != l_l2sync_clock) && - ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECLKSYNC_TIMEOUT().set_EQPPMQACSR(l_data64), + ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_CLK_SYNC_TIMEOUT() + .set_EQ_QPPM_QACSR(l_data64) + .set_CACHE_CLK_SYNC_POLL_DELAY_HW_NS(CACHE_CLK_SYNC_POLL_DELAY_HW_NS) + .set_CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS(CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS) + .set_CACHE_TARGET(i_target), "EX-L2 Clock Sync Timeout"); FAPI_DBG("EX-L2 clock sync done"); @@ -278,24 +294,30 @@ p9_hcd_cache_startclocks( FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_UNSET(7))); FAPI_TRY(fapi2::delay( - CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + CACHE_CPLT_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * p9hcd::CLK_PERIOD_250PS / 1000, - CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + CACHE_CPLT_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * p9hcd::SIM_CYCLE_4U4D)); FAPI_DBG("Poll for cache chiplet aligned"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CACHE_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS / + CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS; do { FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); - } - while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0)); - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECPLTALIGN_TIMEOUT() - .set_EQCPLTSTAT0(l_data64), + fapi2::delay(CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS, + CACHE_CPLT_ALIGN_POLL_DELAY_SIM_CYCLE); + } + while((l_data64.getBit<9>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_CPLT_ALIGN_TIMEOUT() + .set_EQ_CPLT_STAT0(l_data64) + .set_CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS(CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS) + .set_CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS(CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS) + .set_CACHE_TARGET(i_target), "Cache Chiplets Aligned Timeout"); FAPI_DBG("Cache chiplets aligned now"); @@ -316,24 +338,33 @@ p9_hcd_cache_startclocks( FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); FAPI_DBG("Poll for cache clocks running via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CACHE_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = CACHE_CLK_START_POLL_TIMEOUT_HW_NS / + CACHE_CLK_START_POLL_DELAY_HW_NS; do { + fapi2::delay(CACHE_CLK_START_POLL_DELAY_HW_NS, + CACHE_CLK_START_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + while((l_data64.getBit<8>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CACHE_CLK_START_TIMEOUT() + .set_EQ_CPLT_STAT(l_data64) + .set_CACHE_CLK_START_POLL_DELAY_HW_NS(CACHE_CLK_START_POLL_DELAY_HW_NS) + .set_CACHE_CLK_START_POLL_TIMEOUT_HW_NS(CACHE_CLK_START_POLL_TIMEOUT_HW_NS) + .set_CACHE_TARGET(i_target), "Cache Clock Start Timeout"); FAPI_DBG("Check cache clocks running"); FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); FAPI_ASSERT(((l_data64 & l_region_clock) == 0), - fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), + fapi2::CACHE_CLK_START_FAILED() + .set_EQ_CLK_STAT(l_data64) + .set_CACHE_TARGET(i_target), "Cache Clock Start Failed"); FAPI_DBG("Cache clocks running now"); @@ -352,7 +383,9 @@ p9_hcd_cache_startclocks( FAPI_DBG("Check the Global Checkstop FIR of Cache Chiplet"); FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64)); FAPI_ASSERT(((l_data64 & BITS64(0, 27)) == 0), - fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64), + fapi2::CACHE_CHECKSTOP_AFTER_CLK_START() + .set_EQ_XFIR(l_data64) + .set_CACHE_TARGET(i_target), "Cache Chiplet Checkstop"); #ifndef __PPE__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H index c5ffc609..1f486804 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Quad Clock Start /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:SGPE -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_STARTCLOCKS_H__ #define __P9_HCD_CACHE_STARTCLOCKS_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C index 1726fd59..b203275d 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C @@ -30,12 +30,12 @@ /// Use ABIST engine to zero out all arrays /// Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H index cc8daf0b..5ab015b4 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core Initialize arrays /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_ARRAYINIT_H__ #define __P9_HCD_CORE_ARRAYINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C index d954b97d..72bcafd4 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,12 +34,12 @@ /// DCCs and SkewAdjust starts aligning clocks /// Scan0 flush all chiplet rings except VITAL, GPTR and TIME -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -63,29 +63,9 @@ p9_hcd_core_chiplet_init( const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) { FAPI_INF(">>p9_hcd_core_chiplet_init"); - /* - #ifndef P9_HCD_STOP_SKIP_FLUSH - //-------------------------------------------- - // perform scan0 module for pervasive chiplet - //-------------------------------------------- - // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest - // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has - // all stumps less than 8191, the loop can be removed. - fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = - i_target.getParent<fapi2::TARGET_TYPE_PERV>(); - FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings"); - for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) - FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, - p9hcd::SCAN0_REGION_PERV_CORE, - p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); - - fapi_try_exit: - - #endif - */ FAPI_INF("<<p9_hcd_core_chiplet_init"); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H index 00896101..3826281e 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core Flush/Initialize /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_CHIPLET_INIT_H__ #define __P9_HCD_CORE_CHIPLET_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C index a9df9858..b8cf91df 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C @@ -35,12 +35,12 @@ /// - Drop glsmux async reset /// Scan0 flush entire core chiplet -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H index e2f2d206..e4ff11f8 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core Chiplet Reset /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_CHIPLET_RESET_H__ #define __P9_HCD_CORE_CHIPLET_RESET_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C index d4ebc8a8..a713f45d 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C @@ -35,12 +35,12 @@ /// Check for the presence of core override TIME ring from image; /// if found, apply; if not, apply core base TIME from image -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H index e162d0e2..ea503a73 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Load Core GPTR and Time rings /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_GPTR_TIME_INIT_H__ #define __P9_HCD_CORE_GPTR_TIME_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C index 733cb5dc..387e1853 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C @@ -35,12 +35,12 @@ /// Note : if in fused mode, both core rings will be initialized to the same /// values via multicast scans -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H index ca278ec2..93f5a976 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core scan init /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_INITF_H__ #define __P9_HCD_CORE_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C index 64f1933b..884bdb77 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C @@ -26,12 +26,6 @@ /// @file p9_hcd_core_occ_runtime_scom.C /// @brief Core OCC runtime SCOMS /// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:CME -/// *HWP Level : 1 -/// /// Procedure Summary: /// Run-time updates from OCC code that are put somewhere revisit with OCC FW team /// OCC FW sets up value in the TBD SCOM section @@ -39,55 +33,35 @@ /// Placeholder at this point /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 3 + //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- -#include <fapi2.H> -//#include <common_scom_addresses.H> -//will be replaced with real scom address header file + #include "p9_hcd_core_occ_runtime_scom.H" //----------------------------------------------------------------------------- // Constant Definitions //----------------------------------------------------------------------------- -#define host_runtime_scom 0 //----------------------------------------------------------------------------- // Procedure: Core OCC runtime SCOMS //----------------------------------------------------------------------------- -extern "C" +fapi2::ReturnCode +p9_hcd_core_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) { + FAPI_INF(">>p9_hcd_core_occ_runtime_scom"); - fapi2::ReturnCode - p9_hcd_core_occ_runtime_scom( - const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) - { - -#if 0 - - fapi2::buffer<uint64_t> data; - - // Run the SCOM sequence if the SCOM procedure is defined - // - la A0, occ_runtime_scom - // - ld D0, 0, A0 - // - braz D0, 1f - //FAPI_INF("Launching OCC Runtime SCOM routine") - // - bsrd D0 - // - 1: - - return fapi2::FAPI2_RC_SUCCESS; - - FAPI_CLEANUP(); - return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; - -#endif - - return fapi2::FAPI2_RC_SUCCESS; - - } // Procedure - - -} // extern C + FAPI_INF("<<p9_hcd_core_occ_runtime_scom"); + return fapi2::FAPI2_RC_SUCCESS; +} diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H index c6f77b9f..d40a4401 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,25 +26,26 @@ /// @file p9_hcd_core_occ_runtime_scom.H /// @brief Core OCC runtime SCOMS /// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:CME -/// *HWP Level : 1 -/// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 3 #ifndef __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ #define __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ -extern "C" -{ +#include <fapi2.H> /// @typedef p9_hcd_core_occ_runtime_scom_FP_t /// function pointer typedef definition for HWP call support - typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) ( - const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); +typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); +extern "C" +{ /// @brief Core OCC runtime SCOMS /// @@ -58,7 +59,6 @@ extern "C" p9_hcd_core_occ_runtime_scom( const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); - -} // extern C +} #endif // __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C index b7574f62..28340aba 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C @@ -37,9 +37,9 @@ /// Nop (as the CME is not running in bringing up the first Core) /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME // *HWP Level : 2 @@ -47,6 +47,7 @@ //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- + #include <p9_quad_scom_addresses.H> #include <p9_hcd_common.H> #include "p9_hcd_core_pcb_arb.H" @@ -55,7 +56,6 @@ // Constant Definitions: Core Chiplet PCB Arbitration //----------------------------------------------------------------------------- - fapi2::ReturnCode p9_hcd_core_pcb_arb( const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H index aa6c6c1d..593f3a58 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,9 +27,9 @@ /// @brief Core Chiplet PCB Arbitration /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME // *HWP Level : 2 diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C index 5dda8e1d..b0928b56 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,12 +32,12 @@ /// Check for valid power on completion, via getscom from CPPM /// Polled Timeout: 100us -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H index 8528c491..50df2c6f 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core Chiplet Power-on /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_POWERON_H__ #define __P9_HCD_CORE_POWERON_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C index fe760e5c..059969d0 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,13 +24,7 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_core_ras_runtime_scom.C -/// @brief FSP/Host run-time SCOMS -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:CME -/// *HWP Level : 1 +/// @brief Core FSP/Host run-time SCOMS /// /// Procedure Summary: /// Run-time updates from FSP based PRD, etc that are put on the core image @@ -44,122 +38,37 @@ /// Restore Hypervisor, Host PRD, etc. SCOMs /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 3 + //----------------------------------------------------------------------------- // Includes //----------------------------------------------------------------------------- -#include <fapi2.H> -//#include <common_scom_addresses.H> -//will be replaced with real scom address header file + #include "p9_hcd_core_ras_runtime_scom.H" //----------------------------------------------------------------------------- // Constant Definitions //----------------------------------------------------------------------------- -#define host_runtime_scom 0 //----------------------------------------------------------------------------- -// Procedure: FSP/Host run-time SCOMS +// Procedure: Core FSP/Host run-time SCOMS //----------------------------------------------------------------------------- -extern "C" +fapi2::ReturnCode +p9_hcd_core_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) { + FAPI_INF(">>p9_hcd_core_ras_runtime_scom"); - fapi2::ReturnCode - p9_hcd_core_ras_runtime_scom( - const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) - { - -#if 0 - fapi2::buffer<uint64_t> data; - - // Run the SCOM sequence if the SCOM procedure is defined - // - la A0, sp_runtime_scom - // - ld D0, 0, A0 - // - braz D0, 1f - //FAPI_INF("Launching SP Runtime SCOM routine") - // - bsrd D0 - // - 1: - // - - // Run the SCOM sequence if the SCOM procedure is defined. - // - la A0, host_runtime_scom - // - ld D1, 0, A0 - // - braz D1, 1f - - // Prep P1 - // - setp1_mcreadand D0 -#if 0 - // Disable the AISS to allow the override - // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // - andi D0, D0, ~(BIT(1)) - // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 - // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts - // RAMs (SCOMs actually) in the IPL "Nap" state - // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // - ori D0, D0, (BIT(15)) - // - andi D0, D0, ~(BIT(21)) - // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 -#endif - // Branch to sub_slw_runtime_scom() - FAPI_INF("Launching Host Runtime SCOM routine") - // - bsrd D1 - - // Prep P1 - // - setp1_mcreadand D0 -#if 0 - // Clear regular wake-up and restore PSCOM fence in OHA - // These were established in p9_sbe_ex_scominit.S - // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // - andi D0, D0, ~(BIT(15)) - // - ori D0, D0, BIT(21) - // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 - // Enable the AISS to allow further operation - // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // - ori D0, D0, (BIT(1)) - // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 -#endif - // - bra 2f - // - 1: - // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped - // - setp1_mcreadand D0 -#if 0 - // Clear regular wake-up and restore PSCOM fence in OHA - // These were established in p9_sbe_ex_scominit.S - // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // - andi D0, D0, ~BIT(1) - // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 - // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 - // - andi D0, D0, ~(BIT(15)) - // - ori D0, D0, BIT(21) - // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 - // Enable the AISS to allow further operation - // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 - // - ori D0, D0, (BIT(1)) - // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 -#endif - // - 2: - - // If using cv_multicast, we need to set the magic istep number here - // - la A0, p9_sbe_select_ex_control - // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX - // - braz D0, 3f - FAPI_DBG("Setting istep num to magic number because cv_multicast is set") - // - lpcs P1, MBOX_SBEVITAL_0x0005001C - // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) - // - 3: - - return fapi2::FAPI2_RC_SUCCESS; - - FAPI_CLEANUP(); - return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; - -#endif - - return fapi2::FAPI2_RC_SUCCESS; - - } // Procedure + FAPI_INF("<<p9_hcd_core_ras_runtime_scom"); + return fapi2::FAPI2_RC_SUCCESS; +} -} // extern C diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H index 65657c1d..45834217 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,28 +24,30 @@ /* IBM_PROLOG_END_TAG */ /// /// @file p9_hcd_core_ras_runtime_scom.H -/// @brief FSP/Host run-time SCOMS -/// -/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> -/// *HWP Team : PM -/// *HWP Consumed by : SBE:CME -/// *HWP Level : 1 +/// @brief Core FSP/Host run-time SCOMS /// +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 3 + #ifndef __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ #define __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ -extern "C" -{ +#include <fapi2.H> /// @typedef p9_hcd_core_ras_runtime_scom_FP_t /// function pointer typedef definition for HWP call support - typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) ( - const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); +typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); +extern "C" +{ -/// @brief FSP/Host run-time SCOMS +/// @brief Core FSP/Host run-time SCOMS /// /// @param [in] i_target TARGET_TYPE_CORE target // @@ -57,7 +59,6 @@ extern "C" p9_hcd_core_ras_runtime_scom( const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); - -} // extern C +} #endif // __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C index ec8f73db..4e81c2d8 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,12 +34,12 @@ /// in MVPD, but SBE image is customized with rings for booting cores /// at build time -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H index bd510b03..070ee90a 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Load Repair ring for core /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_REPAIR_INITF_H__ #define __P9_HCD_CORE_REPAIR_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C index 307010ca..6e0c58f5 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C @@ -35,12 +35,12 @@ /// Else call the function at the pointer; /// pointer is filled in by XIP Customization -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H index 68c4609a..60135e82 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H @@ -27,12 +27,12 @@ /// @brief Core Customization SCOMs /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_SCOMCUST_H__ #define __P9_HCD_CORE_SCOMCUST_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C index 97572706..9275e520 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C @@ -30,12 +30,12 @@ /// Apply any coded SCOM initialization to core /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //----------------------------------------------------------------------------- // Includes diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H index 9e6434b4..c770225d 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core SCOM Inits /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_SCOMINIT_H__ #define __P9_HCD_CORE_SCOMINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index 844e3064..cd08560c 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -50,12 +50,12 @@ /// (Done) Clear flushmode_inh to go into flush mode /// (Done) Check cache/core chiplet_is_aligned -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -71,9 +71,18 @@ enum P9_HCD_CORE_STARTCLOCKS_CONSTANTS { - CORE_CLK_SYNC_TIMEOUT_IN_MS = 1, - CORE_CLK_START_TIMEOUT_IN_MS = 1, - CORE_CLK_ALIGN_DELAY_CACHE_CYCLES = 255 + CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CORE_CLK_SYNC_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CORE_CLK_SYNC_POLL_DELAY_SIM_CYCLE = 32000, // 320k sim cycle delay + + CORE_CPLT_ALIGN_DELAY_CACHE_CYCLES = 255, // in cache cycles + CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CORE_CPLT_ALIGN_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CORE_CPLT_ALIGN_POLL_DELAY_SIM_CYCLE = 32000, // 320k sim cycle delay + + CORE_CLK_START_POLL_TIMEOUT_HW_NS = 1000000, // 10^6ns = 1ms timeout + CORE_CLK_START_POLL_DELAY_HW_NS = 10000, // 10us poll loop delay + CORE_CLK_START_POLL_DELAY_SIM_CYCLE = 32000 // 320k sim cycle delay }; //------------------------------------------------------------------------------ @@ -86,7 +95,7 @@ p9_hcd_core_startclocks( { FAPI_INF(">>p9_hcd_core_startclocks"); fapi2::buffer<uint64_t> l_data64; - uint32_t l_timeout; + uint32_t l_poll_loops; uint32_t l_attr_system_id = 0; uint8_t l_attr_group_id = 0; uint8_t l_attr_chip_id = 0; @@ -169,17 +178,24 @@ p9_hcd_core_startclocks( FAPI_TRY(putScom(i_target, C_CPPM_CACCR_OR, MASK_SET(15))); FAPI_DBG("Poll for core clock sync done via CPPM_CACSR[13]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CORE_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS / + CORE_CLK_SYNC_POLL_DELAY_HW_NS; do { + fapi2::delay(CORE_CLK_SYNC_POLL_DELAY_HW_NS, + CORE_CLK_SYNC_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, C_CPPM_CACSR, l_data64)); } - while((l_data64.getBit<13>() != 1) && ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CORECLKSYNC_TIMEOUT().set_COREPPMCACSR(l_data64), + while((l_data64.getBit<13>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CORE_CLK_SYNC_TIMEOUT() + .set_CORE_CPPM_CACSR(l_data64) + .set_CORE_CLK_SYNC_POLL_DELAY_HW_NS(CORE_CLK_SYNC_POLL_DELAY_HW_NS) + .set_CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS(CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS) + .set_CORE_TARGET(i_target), "Core Clock Sync Timeout"); FAPI_DBG("Core clock sync done"); @@ -218,24 +234,30 @@ p9_hcd_core_startclocks( FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_UNSET(7))); FAPI_TRY(fapi2::delay( - CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + CORE_CPLT_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * p9hcd::CLK_PERIOD_250PS / 1000, - CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + CORE_CPLT_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * p9hcd::SIM_CYCLE_4U4D)); FAPI_DBG("Poll for core chiplet aligned"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CORE_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS / + CORE_CPLT_ALIGN_POLL_DELAY_HW_NS; do { FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64)); - } - while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0)); - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CORECPLTALIGN_TIMEOUT() - .set_CORECPLTSTAT0(l_data64), + fapi2::delay(CORE_CPLT_ALIGN_POLL_DELAY_HW_NS, + CORE_CPLT_ALIGN_POLL_DELAY_SIM_CYCLE); + } + while((l_data64.getBit<9>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CORE_CPLT_ALIGN_TIMEOUT() + .set_CORE_CPLT_STAT0(l_data64) + .set_CORE_CPLT_ALIGN_POLL_DELAY_HW_NS(CORE_CPLT_ALIGN_POLL_DELAY_HW_NS) + .set_CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS(CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS) + .set_CORE_TARGET(i_target), "Core Chiplets Aligned Timeout"); FAPI_DBG("Core chiplets aligned now"); @@ -259,24 +281,33 @@ p9_hcd_core_startclocks( FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64)); FAPI_DBG("Poll for core clocks running via CPLT_STAT0[8]"); - l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * - CORE_CLK_START_TIMEOUT_IN_MS; + l_poll_loops = CORE_CLK_START_POLL_TIMEOUT_HW_NS / + CORE_CLK_START_POLL_DELAY_HW_NS; do { + fapi2::delay(CORE_CLK_START_POLL_DELAY_HW_NS, + CORE_CLK_START_POLL_DELAY_SIM_CYCLE); + FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); - - FAPI_ASSERT((l_timeout != 0), - fapi2::PMPROC_CORECLKSTART_TIMEOUT().set_CORECPLTSTAT(l_data64), + while((l_data64.getBit<8>() != 1) && ((--l_poll_loops) != 0)); + + FAPI_ASSERT((l_poll_loops != 0), + fapi2::CORE_CLK_START_TIMEOUT() + .set_CORE_CPLT_STAT(l_data64) + .set_CORE_CLK_START_POLL_DELAY_HW_NS(CORE_CLK_START_POLL_DELAY_HW_NS) + .set_CORE_CLK_START_POLL_TIMEOUT_HW_NS(CORE_CLK_START_POLL_TIMEOUT_HW_NS) + .set_CORE_TARGET(i_target), "Core Clock Start Timeout"); FAPI_DBG("Check core clocks running via CLOCK_STAT_SL[4-13]"); FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64)); FAPI_ASSERT(((l_data64 & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0), - fapi2::PMPROC_CORECLKSTART_FAILED().set_CORECLKSTAT(l_data64), + fapi2::CORE_CLK_START_FAILED() + .set_CORE_CLK_STAT(l_data64) + .set_CORE_TARGET(i_target), "Core Clock Start Failed"); FAPI_DBG("Core clocks running now"); @@ -303,7 +334,9 @@ p9_hcd_core_startclocks( FAPI_DBG("Check the Global Checkstop FIR of Core Chiplet"); FAPI_TRY(getScom(i_target, C_XFIR, l_data64)); FAPI_ASSERT(((l_data64 & BITS64(0, 27)) == 0), - fapi2::PMPROC_CORE_XSTOP().set_COREXFIR(l_data64), + fapi2::CORE_CHECKSTOP_AFTER_CLK_START() + .set_CORE_XFIR(l_data64) + .set_CORE_TARGET(i_target), "Core Chiplet Checkstop"); #ifndef __PPE__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H index 514d52e4..43155d89 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,12 +27,12 @@ /// @brief Core Clock Start /// -// *HWP HWP Owner : David Du <daviddu@us.ibm.com> -// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> -// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com> // *HWP Team : PM // *HWP Consumed by : SBE:CME -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CORE_STARTCLOCKS_H__ #define __P9_HCD_CORE_STARTCLOCKS_H__ diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml index 9c1c1af3..547e4c29 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -27,102 +27,100 @@ <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc> + <rc>RC_CACHE_DPLL_LOCK_TIMEOUT</rc> <description> DPLL is not locking. </description> - <ffdc>EQQPPMDPLLSTAT</ffdc> + <ffdc>EQ_QPPM_DPLL_STAT</ffdc> + <ffdc>DPLL_LOCK_POLL_DELAY_HW_NS</ffdc> + <ffdc>DPLL_LOCK_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc> + <rc>RC_CACHE_DPLL_CLK_START_TIMEOUT</rc> <description> dpll clock start timed out. </description> - <ffdc>EQCPLTSTAT</ffdc> + <ffdc>EQ_CPLT_STAT</ffdc> + <ffdc>DPLL_START_POLL_DELAY_HW_NS</ffdc> + <ffdc>DPLL_START_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc> + <rc>RC_CACHE_DPLL_CLK_START_FAILED</rc> <description> dpll clock start failed. </description> - <ffdc>EQCLKSTAT</ffdc> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <sbeError/> - <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc> - <description> - anep clock start timed out. - </description> - <ffdc>EQCPLTSTAT</ffdc> + <ffdc>EQ_CLK_STAT</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml index e5fce113..9d1042e1 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml @@ -26,11 +26,12 @@ <hwpErrors> <!-- ********************************************************************* --> <hwpError> - <rc>RC_P9_HCD_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL</rc> + <rc>RC_NDD1_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL</rc> <description> - Data mis-match on EQ_SCAN64 + Data mis-match on EQ_SCAN64, for Nimbus DD1 MPIPL workaround only </description> <ffdc>EQ_SCAN64_VAL</ffdc> + <ffdc>CACHE_TARGET</ffdc> </hwpError> <!-- ********************************************************************* --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml index 16abe42c..174185fe 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_scominit_errors.xml @@ -27,11 +27,23 @@ <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHESCOMINIT_NOGOODCOREINEX</rc> + <rc>RC_CACHE_SCOMINIT_NO_GOOD_CORE_IN_EX</rc> <description> no partial good core in partial good ex, check qcsr configuration </description> <ffdc>QCSR</ffdc> + <ffdc>CACHE_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> </hwpError> <!-- ********************************************************************* --> </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml index 789757c4..6e66cbf5 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -27,67 +27,170 @@ <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHECPLTALIGN_TIMEOUT</rc> + <rc>RC_CACHE_CPLT_ALIGN_TIMEOUT</rc> <description> cache chiplets alignment timed out. </description> - <ffdc>EQCPLTSTAT0</ffdc> + <ffdc>EQ_CPLT_STAT0</ffdc> + <ffdc>CACHE_CPLT_ALIGN_POLL_DELAY_HW_NS</ffdc> + <ffdc>CACHE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHE_XSTOP</rc> + <rc>RC_CACHE_CHECKSTOP_AFTER_CLK_START</rc> <description> - cache checkstops. + cache chiplet detects a checkstop after cache chiplet clock starts. </description> - <ffdc>EQXFIR</ffdc> + <ffdc>EQ_XFIR</ffdc> + <ffdc>CACHE_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>MEDIUM</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHECLKSYNC_TIMEOUT</rc> + <rc>RC_CACHE_CLK_SYNC_TIMEOUT</rc> <description> L2 EXs clock sync done timed out. </description> - <ffdc>EQPPMQACSR</ffdc> + <ffdc>EQ_QPPM_QACSR</ffdc> + <ffdc>CACHE_CLK_SYNC_POLL_DELAY_HW_NS</ffdc> + <ffdc>CACHE_CLK_SYNC_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHECLKSTART_FAILED</rc> + <rc>RC_CACHE_CLK_START_FAILED</rc> <description> cache clock start failed. </description> - <ffdc>EQCLKSTAT</ffdc> + <ffdc>EQ_CLK_STAT</ffdc> + <ffdc>CACHE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CACHECLKSTART_TIMEOUT</rc> + <rc>RC_CACHE_CLK_START_TIMEOUT</rc> <description> cache clock start timed out. </description> - <ffdc>EQCPLTSTAT</ffdc> + <ffdc>EQ_CPLT_STAT</ffdc> + <ffdc>CACHE_CLK_START_POLL_DELAY_HW_NS</ffdc> + <ffdc>CACHE_CLK_START_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CACHE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_EQ</childType> + <childNumber>EQ_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml index 9790d7ce..dd845997 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -27,85 +27,202 @@ <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORECPLTALIGN_TIMEOUT</rc> + <rc>RC_CORE_CPLT_ALIGN_TIMEOUT</rc> <description> core chiplets alignment timed out. </description> - <ffdc>CORECPLTSTAT0</ffdc> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <sbeError/> - <rc>RC_PMPROC_QUADCPLTALIGN_FAILED</rc> - <description> - quad chiplets alignment failed. - </description> - <ffdc>QUADCPLTSTAT0</ffdc> + <ffdc>CORE_CPLT_STAT0</ffdc> + <ffdc>CORE_CPLT_ALIGN_POLL_DELAY_HW_NS</ffdc> + <ffdc>CORE_CPLT_ALIGN_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CORE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORECPLTALIGN_FAILED</rc> + <rc>RC_CORE_CPLT_ALIGN_FAILED</rc> <description> core chiplets alignment failed. </description> - <ffdc>CORECPLTSTAT0</ffdc> + <ffdc>CORE_CPLT_STAT0</ffdc> + <ffdc>CORE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORE_XSTOP</rc> + <rc>RC_CORE_CHECKSTOP_AFTER_CLK_START</rc> <description> - core checkstops. + core chiplet detects a checkstop after core chiplet clock starts. </description> - <ffdc>COREXFIR</ffdc> + <ffdc>CORE_XFIR</ffdc> + <ffdc>CORE_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>MEDIUM</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORECLKSYNC_TIMEOUT</rc> + <rc>RC_CORE_CLK_SYNC_TIMEOUT</rc> <description> core clock sync done timed out. </description> - <ffdc>COREPPMCACSR</ffdc> + <ffdc>CORE_CPPM_CACSR</ffdc> + <ffdc>CORE_CLK_SYNC_POLL_DELAY_HW_NS</ffdc> + <ffdc>CORE_CLK_SYNC_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CORE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORECLKSTART_FAILED</rc> + <rc>RC_CORE_CLK_START_FAILED</rc> <description> core clock start failed. </description> - <ffdc>CORECLKSTAT</ffdc> + <ffdc>CORE_CLK_STAT</ffdc> + <ffdc>CORE_TARGET</ffdc> + <callout> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + <priority>HIGH</priority> + </callout> + <deconfigure> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </deconfigure> + <gard> + <childTargets> + <parent>PROC_CHIP_IN_ERROR</parent> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> + </childTargets> + </gard> </hwpError> <!-- ********************************************************************* --> <hwpError> <sbeError/> - <rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc> + <rc>RC_CORE_CLK_START_TIMEOUT</rc> <description> core clock start timed out. </description> - <ffdc>CORECPLTSTAT</ffdc> + <ffdc>CORE_CPLT_STAT</ffdc> + <ffdc>CORE_CLK_START_POLL_DELAY_HW_NS</ffdc> + <ffdc>CORE_CLK_START_POLL_TIMEOUT_HW_NS</ffdc> + <ffdc>CORE_TARGET</ffdc> <callout> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> </childTargets> <priority>HIGH</priority> </callout> <deconfigure> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> </childTargets> </deconfigure> <gard> <childTargets> <parent>PROC_CHIP_IN_ERROR</parent> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childNumber>EX_NUMBER_IN_ERROR</childNumber> + <childType>TARGET_TYPE_CORE</childType> + <childNumber>CORE_NUMBER_IN_ERROR</childNumber> </childTargets> </gard> </hwpError> |
