diff options
author | Ashish <ashish.more@in.ibm.com> | 2016-08-24 07:23:04 -0400 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-10-05 06:12:07 -0400 |
commit | 1878aa7b58d6f2279a0149d7931bed4b43f5fd50 (patch) | |
tree | 1c1a9c3ed1078a4550aae40b852e1244d5a0f2a3 /src/import/chips | |
parent | e98d926ff7cf4a0d1a4a1a722bb8802f8f075df5 (diff) | |
download | talos-sbe-1878aa7b58d6f2279a0149d7931bed4b43f5fd50.tar.gz talos-sbe-1878aa7b58d6f2279a0149d7931bed4b43f5fd50.zip |
PPE command line control
Change-Id: Idaabcdd1ab3e6e919e865f364cf912f4752626e0
Original-Change-Id: I467470a2a8832dc1ada7568cd3773ee53d61cbe9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28719
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48006
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C | 485 |
1 files changed, 485 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C new file mode 100644 index 00000000..7a80ca31 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C @@ -0,0 +1,485 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_ppe_utils.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_ppe_utils.C +/// @brief PPE commonly used functions +/// +/// *HWP HW Owner : Ashish More <ashish.more.@in.ibm.com> +/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Level : 2 +/// *HWP Consumed by : SBE, Cronus +/// +/// @verbatim +/// +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include <p9_ppe_utils.H> +#include <p9_hcd_common.H> + +/** + * @brief enumerates opcodes for few instructions. + */ +enum +{ + OPCODE_31 = 31, + MTSPR_CONST1 = 467, + MTSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MTSPR_CONST1 << (31 - 30)), + MFSPR_CONST1 = 339, + MFSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MFSPR_CONST1 << (31 - 30)), + MFMSRD_CONST1 = 83, + MFCR_CONST1 = 19, + ANDIS_CONST = 29, + ORIS_CONST = 25, +}; + +// Vector defining the special acceess egisters +std::vector<PPEReg_t> v_ppe_special_regs = +{ + { MSR, "MSR" }, + { CR, "CR" }, +}; + +// Vector defining the major SPRs +// Note: SPRG0 is not include as it is saved and restored as the means for +// accessing the other SPRS +std::vector<PPEReg_t> v_ppe_major_sprs = +{ + { CTR, "CTR" }, + { LR, "LR" }, + { ISR, "ISR" }, + { SRR0, "SRR0" }, + { SRR1, "SRR1" }, + { TCR, "TCR" }, + { TSR, "TSR" }, +}; + +// Vector defining the minor SPRs +std::vector<PPEReg_t> v_ppe_minor_sprs = +{ + { DACR, "DACR" }, + { DBCR, "DBCR" }, + { DEC, "DEC" }, + { IVPR, "IVPR" }, + { PIR, "PIR" }, + { PVR, "PVR" }, + { XER, "XER" }, +}; + +// Vector defining the GPRs +std::vector<PPEReg_t> v_ppe_gprs = +{ + { R0, "R0" }, + { R1, "R1" }, + { R2, "R2" }, + { R3, "R3" }, + { R4, "R4" }, + { R5, "R5" }, + { R6, "R6" }, + { R7, "R7" }, + { R8, "R8" }, + { R9, "R9" }, + { R10, "R10" }, + { R13, "R13" }, + { R28, "R28" }, + { R29, "R29" }, + { R30, "R30" }, + { R31, "R31" }, +}; + + + +//----------------------------------------------------------------------------- + +/** + * @brief generates a PPE instruction for some formats + * @param[in] i_Op Opcode + * @param[in] i_Rts Source or Target Register + * @param[in] i_RA Address Register + * @param[in] i_d Instruction Data Field + * @return returns 32 bit instruction representing the PPE instruction. + */ + +uint32_t ppe_getInstruction( const uint16_t i_Op, const uint16_t i_Rts, const uint16_t i_Ra, const uint16_t i_d) +{ + uint32_t instOpcode = 0; + + instOpcode = (i_Op & 0x3F) << (31 - 5); + instOpcode |= (i_Rts & 0x1F) << (31 - 10); + instOpcode |= (i_Ra & 0x1F) << (31 - 15); + instOpcode |= (i_d & 0xFFFF) << (31 - 31); + + return instOpcode; +} +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mtspr + * @param[in] i_Rs source register number + * @param[in] i_Spr represents spr where data is to be moved. + * @return returns 32 bit instruction representing mtspr instruction. + */ +uint32_t ppe_getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) +{ + uint32_t mtsprInstOpcode = 0; + uint32_t temp = (( i_Spr & 0x03FF ) << 11); + mtsprInstOpcode = ( temp & 0x0000F800 ) << 5; + mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; + mtsprInstOpcode |= MTSPR_BASE_OPCODE; + mtsprInstOpcode |= ( i_Rs & 0x001F ) << 21; + + return mtsprInstOpcode; +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mfspr + * @param[in] i_Rt target register number + * @param[in] i_Spr represents spr where data is to sourced + * @return returns 32 bit instruction representing mfspr instruction. + */ +uint32_t ppe_getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_Spr ) +{ + uint32_t mtsprInstOpcode = 0; + uint32_t temp = (( i_Spr & 0x03FF ) << 11); + mtsprInstOpcode = ( temp & 0x0000F800 ) << 5; + mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5; + mtsprInstOpcode |= MFSPR_BASE_OPCODE; + mtsprInstOpcode |= ( i_Rt & 0x001F ) << 21; + + return mtsprInstOpcode; +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mfmsr instruction. + * @param[in] i_Rt target register number + * @return returns 32 bit instruction representing mfmsr instruction. + * @note moves contents of register MSR to i_Rt register. + */ +uint32_t ppe_getMfmsrInstruction( const uint16_t i_Rt ) +{ + uint32_t mfmsrdInstOpcode = 0; + mfmsrdInstOpcode = 0; + mfmsrdInstOpcode = OPCODE_31 << 26; + mfmsrdInstOpcode |= i_Rt << 21 | ( MFMSRD_CONST1 << 1 ); + + return mfmsrdInstOpcode; +} + +//----------------------------------------------------------------------------- + +/** + * @brief generates instruction for mfcr instruction. + * @param[in] i_Rt target register number + * @return returns 32 bit instruction representing mfcr instruction. + * @note moves contents of register CR to i_Rt register. + */ +uint32_t ppe_getMfcrInstruction( const uint16_t i_Rt ) +{ + uint32_t mfcrdInstOpcode = 0; + mfcrdInstOpcode = 0; + mfcrdInstOpcode = OPCODE_31 << 26; + mfcrdInstOpcode |= i_Rt << 21 | ( MFCR_CONST1 << 1 ); + + return mfcrdInstOpcode; +} + +//----------------------------------------------------------------------------- + +/** + * @brief poll for Halt state + * @param[in] i_Rt target register number + * @return fapi2::ReturnCode + * @note moves contents of register MSR to i_Rt register. + */ +fapi2::ReturnCode ppe_pollHaltState( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address) +{ + fapi2::buffer<uint64_t> l_data64; + + // Halt state entry should be very fast on PPEs (eg nanoseconds) + // Try only using the SCOM access time to delay. + static const uint32_t HALT_TRIES = 10; + + uint32_t l_timeout_count = HALT_TRIES; + + do + { + FAPI_TRY(getScom(i_target, i_base_address + PPE_XIRAMDBG, l_data64), "Error in GETSCOM"); + } + while (! l_data64.getBit<0>() && + --l_timeout_count != 0); + + + FAPI_ASSERT(l_data64.getBit<0>(), fapi2::P9_PPE_STATE_HALT_TIMEOUT_ERR(), + "PPE Halt Timeout"); + + +fapi_try_exit: + return fapi2::current_err; +} + +//----------------------------------------------------------------------------- + +/** + * @brief halt the engine + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs XCR with halt bit to halt the engine. + */ +fapi2::ReturnCode ppe_halt( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address) +{ + fapi2::buffer<uint64_t> l_data64; + + FAPI_INF(" Send HALT command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); + + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), "Error in PUTSCOM in XCR to generate Halt condition"); + + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + +fapi_try_exit: + return fapi2::current_err; +} +//----------------------------------------------------------------------------- + +/** + * @brief force halt the engine + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs XCR with force halt to force halt the engine. + */ +fapi2::ReturnCode ppe_force_halt( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address) +{ + fapi2::buffer<uint64_t> l_data64; + + FAPI_INF(" Send FORCE HALT command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::FORCE_HALT, 1, 3); + + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), + "Error in PUTSCOM in XCR to generate Force Halt condition"); + + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + +fapi_try_exit: + return fapi2::current_err; +} +//----------------------------------------------------------------------------- + +/** + * @brief single step the engine + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs XCR with single step tosingle step the engine. + */ +fapi2::ReturnCode ppe_single_step( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address) +{ + fapi2::buffer<uint64_t> l_data64; + + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + FAPI_INF(" Send Single step command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::SINGLE_STEP, 1, 3); + + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), + "Error in PUTSCOM in XCR to generate Single Step condition"); + + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + +fapi_try_exit: + return fapi2::current_err; +} + +//----------------------------------------------------------------------------- + +/** + * @brief resume the halted engine + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs XCR with resume bit to resume the engine. + */ +fapi2::ReturnCode ppe_resume( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address) +{ + fapi2::buffer<uint64_t> l_data64; + + static const uint32_t RESUME_TRIES = 10; + uint32_t l_timeout_count = RESUME_TRIES; + //Before reume always clear debug status (Michael's comment) + FAPI_INF(" Clear debug status via XCR..."); + l_data64.flush<0>(); + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), "Error in PUTSCOM in XCR to resume condition"); + + FAPI_INF(" Send RESUME command via XCR..."); + l_data64.flush<0>().insertFromRight(p9hcd::RESUME, 1, 3); + + FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64), "Error in PUTSCOM in XCR to resume condition"); + + do + { + FAPI_TRY(getScom(i_target, i_base_address + PPE_XIRAMEDR, l_data64)); + FAPI_DBG(" Poll content: XSR: 0x%16llX", l_data64); + } + while((l_data64.getBit<p9hcd::HALTED_STATE>() != 0) && (--l_timeout_count != 0)); + +fapi_try_exit: + return fapi2::current_err; +} +//----------------------------------------------------------------------------- + +/** + * @brief update dbcr + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs mtdbcr + */ +fapi2::ReturnCode ppe_update_dbcr( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address, + const uint64_t l_inst_op, + const uint16_t l_immed_16, + const uint16_t i_Rs) +{ + fapi2::buffer<uint64_t> l_data64; + //Modify DBCR using read modify write + //Move DBCR to Rs + l_data64.flush<0>().insertFromRight(ppe_getMfsprInstruction(i_Rs, DBCR), 0, 32); + FAPI_DBG("getMfsprInstruction(%d, DBCR): 0x%16llX", i_Rs, l_data64 ); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, l_data64)); + //Modify Rs + l_data64.flush<0>().insertFromRight(ppe_getInstruction(l_inst_op, i_Rs, i_Rs, l_immed_16), 0, 32); + FAPI_DBG("getInstruction(Immed %X: 0x%16llX", l_immed_16, l_data64 ); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, l_data64)); + //MOVE new Rs into DBCR + l_data64.flush<0>().insertFromRight(ppe_getMtsprInstruction(i_Rs, DBCR), 0, 32); + FAPI_DBG("getMtsprInstruction(%d, DBCR): 0x%16llX", i_Rs, l_data64 ); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, l_data64)); + +fapi_try_exit: + return fapi2::current_err; +} + +/** + * @brief update dacr + * @param[in] i_target target register number + * @return fapi2::ReturnCode + * @note programs mtdacr + */ +fapi2::ReturnCode ppe_update_dacr( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address, + const uint64_t l_address, + const uint16_t i_Rs) +{ + fapi2::buffer<uint32_t> temp_inst32; + fapi2::buffer<uint64_t> temp_data64; + + temp_data64.flush<0>().insertFromRight(ppe_getMfsprInstruction(i_Rs, SPRG0), 0, 32); + FAPI_DBG("getMfsprInstruction(%d, SPRG0): 0x%16llX", i_Rs, temp_data64 ); + temp_data64.insertFromRight(l_address, 32, 32); + FAPI_DBG("Final Instr + SPRG0: 0x%16llX", temp_data64 ); + //write sprg0 with address and ram mfsprg0 to i_Rs + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMGA, temp_data64 )); + + //then mtdacr from i_Rs + temp_data64.flush<0>().insertFromRight(ppe_getMtsprInstruction(i_Rs, DACR), 0, 32); + FAPI_DBG("getMtsprInstruction(%d, DBCR): 0x%16llX", i_Rs, temp_data64 ); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, temp_data64)); +fapi_try_exit: + return fapi2::current_err; +} +//----------------------------------------------------------------------------- + +/** + * @brief Perform RAM "read" operation + * @param[in] i_target Chip Target + * @param[in] i_base_address Base SCOM address of the PPE + * @param[in] i_instruction RAM instruction to move a register + * @param[out] o_data Returned data + * @return fapi2::ReturnCode + */ +fapi2::ReturnCode ppe_RAMRead( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address, + const fapi2::buffer<uint64_t> i_instruction, + fapi2::buffer<uint32_t>& o_data) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, i_instruction)); + FAPI_DBG(" RAMREAD i_instruction: 0X%16llX", i_instruction); + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + FAPI_TRY(fapi2::getScom(i_target, i_base_address + PPE_XIRAMDBG, l_data64), "Error in GETSCOM"); + l_data64.extractToRight(o_data, 32, 32); + FAPI_DBG(" RAMREAD o_data: 0X%16llX", o_data); + +fapi_try_exit: + return fapi2::current_err; +} +//----------------------------------------------------------------------------- + +/** + * @brief Perform RAM "read" operation + * @param[in] i_target Chip Target + * @param[in] i_base_address Base SCOM address of the PPE + * @param[in] i_instruction RAM instruction to move a register + * @param[out] o_data Returned data + * @return fapi2::ReturnCode + */ +fapi2::ReturnCode ppe_RAM( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_base_address, + const uint64_t i_instruction +) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + + + l_data64.flush<0>().insertFromRight(i_instruction, 0, 32); + FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, l_data64)); + FAPI_DBG(" RAMREAD i_instruction: 0X%16llX", i_instruction); + FAPI_TRY(ppe_pollHaltState(i_target, i_base_address)); + +fapi_try_exit: + return fapi2::current_err; +} + + |