diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2019-05-30 22:44:31 -0400 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-06-14 08:04:00 -0500 |
| commit | e9bc6a014a078762a4b804d5030829fd9165d1f6 (patch) | |
| tree | f445d057ea077cecc5ede4712991a3a104f5c566 /src/import/chips/p9 | |
| parent | e116764a9681dca6fd6d681b550ff0524c3ec275 (diff) | |
| download | talos-sbe-e9bc6a014a078762a4b804d5030829fd9165d1f6.tar.gz talos-sbe-e9bc6a014a078762a4b804d5030829fd9165d1f6.zip | |
p9.filter.pll.scan.initfile -- update CP filter config for p9a
CP refclock input is expected to be 100MHz for p9a
Change-Id: I664dd9122f260fe1abb25c01c813ffadc289f460
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78117
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78120
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 92923b09..11adc315 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -116,6 +116,23 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_CP_FILTER_100MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True where CP refclock is expected to be 100 MHz + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> |
