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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2017-04-22 10:44:20 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-05-29 11:13:39 -0400 |
| commit | 3d1659b34c258027e03d00573b4042e380629622 (patch) | |
| tree | 0b95bc9d6f15640fd865af9c87c45e39c6277230 /src/import/chips/p9 | |
| parent | 9ee125f8832a91160869abbd2c22064c68b2674c (diff) | |
| download | talos-sbe-3d1659b34c258027e03d00573b4042e380629622.tar.gz talos-sbe-3d1659b34c258027e03d00573b4042e380629622.zip | |
Update behavioral description of ATTR_SECURITY_MODE attribute
- Update behavioral description of ATTR_SECURITY_MODE attribute
Change-Id: I34eacb3e541d8cec505713ed2e55a55fd872cbe5
RTC: 170650
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39569
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Dev-Ready: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39573
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index c59e0699..d273bb39 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -462,8 +462,14 @@ <attribute> <id>ATTR_SECURITY_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is - Else ATTR_SECURITY_MODE == 0b0, then clear the SAB bit</description> + <description>SBE context: If SBE image has ATTR_SECURITY_MODE == 0b1, leave + SAB bit as is. Otherwise (ATTR_SECURITY_MODE == 0b0), query mailbox scratch + register 3 bit 6 and if set, clear the SAB bit. Non-SBE context: If + ATTR_SECURITY_MODE == 0b1, do not attempt to clear the SAB bit via the FSI + path. Otherwise (ATTR_SECURITY_MODE == 0b0), attempt to clear the SAB bit + via the FSI path. Customer level chips will silently ignore such a request, + whereas early lab versions may honor it for debug purposes. + </description> <valueType>uint8</valueType> <platInit/> <writeable/> |
