Workaround to fix issue where Powerbus loses track of EQs in DD1

Change-Id: Ia7ffcfdead79e859f21b95be183af05949e68579
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36276
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36277
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

8 files changed, 249 insertions, 7 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
index ce2e5955..9451349a 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -60,13 +60,20 @@ p9_hcd_cache_initf(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
 {
     FAPI_INF(">>p9_hcd_cache_initf");
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
+    fapi2::buffer<uint64_t> l_data64;
+
+#ifdef __PPE__
+    fapi2::buffer<uint64_t>  l_data64_2;
+    uint8_t                 l_isMpipl = 0;
+    uint8_t                 l_isRingSaveMpipl = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+#endif
 
 #ifndef __PPE__
-    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     uint8_t l_attr_system_ipl_phase;
     uint8_t l_attr_runn_mode;
-    fapi2::buffer<uint64_t> l_data64;
-
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys,
                            l_attr_system_ipl_phase));
@@ -76,6 +83,13 @@ p9_hcd_cache_initf(
 
 #endif
 
+#ifdef __PPE__
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_isMpipl),
+             "fapiGetAttribute of ATTR_IS_MPIPL failed!");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
+             "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
+#endif
+
     FAPI_DBG("Scan eq_fure ring");
     FAPI_TRY(fapi2::putRing(i_target, eq_fure),
              "Error from putRing (eq_fure)");
@@ -136,6 +150,93 @@ p9_hcd_cache_initf(
 
 #endif
 
+#ifdef __PPE__
+
+    if (l_isMpipl && l_isRingSaveMpipl)
+    {
+        l_data64.flush<0>();
+        l_data64.setBit<4>();
+        l_data64.setBit<5>();
+        l_data64.setBit<11>();
+        l_data64.setBit<59>();
+
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN_REGION_TYPE,
+                                l_data64));
+
+        l_data64.flush<0>().set(0xa5a5a5a5a5a5a5a5);
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN64,
+                                l_data64));
+
+        for(uint32_t l_spin = 1; l_spin < 10; l_spin++)
+        {
+            /***********G_ring_index***********/
+            //  {0,    0},
+            //  {5039, 0xE000000000000000}, //3
+            //  {5100, 0xC1E061FFED5F0000}, //29
+            //  {5664, 0xE000000000000000}, //3
+            //  {5725, 0xC1E061FFED5F0000}, //29
+            //  {5973, 0xE000000000000000}, //3
+            //  {6034, 0xC1E061FFED5F0000}, //29
+            //  {6282, 0xE000000000000000}, //3
+            //  {6343, 0xC1E061FFED5F0000}, //29
+            //  {17871, 0}
+            /**********************************/
+            uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
+                                  0xE000000000000000 : 0xC1E061FFED5F0000;
+            l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+
+            FAPI_TRY(fapi2::putScom(i_target,
+                                    EQ_SCAN_LONG_ROTATE,
+                                    l_data64));
+            l_data64.flush<0>();
+
+            do
+            {
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_CPLT_STAT0,
+                                        l_data64));
+            }
+            while (l_data64.getBit<8>() == 0);
+
+            l_data64.flush<0>();
+
+            if (l_spin == 9)
+            {
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_SCAN64,
+                                        l_data64));
+
+                if(l_data64 != 0xa5a5a5a5a5a5a5a5)
+                {
+                    FAPI_ASSERT(false,
+                                fapi2::P9_HCD_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL()
+                                .set_EQ_SCAN64_VAL(l_data64),
+                                "Incorrect Value from EQ_SCAN64, Expected Value [0xa5a5a5a5a5a5a5a5]");
+                }
+            }
+            else
+            {
+                l_data64.flush<0>();
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_SCAN64,
+                                        l_data64));
+
+                l_data64_2.set( (l_data64 & ~l_scandata) | G_ring_save[l_spin - 1]);
+                FAPI_TRY(fapi2::putScom(i_target,
+                                        EQ_SCAN64,
+                                        l_data64_2));
+            }
+        }
+
+        l_data64.flush<0>();
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN_REGION_TYPE,
+                                l_data64));
+    }
+
+#endif
 
 fapi_try_exit:
     FAPI_INF("<<p9_hcd_cache_initf");
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
index 08a5b2b7..2934b7d9 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -38,6 +38,7 @@
 #define __P9_HCD_CACHE_INITF_H__
 
 #include <fapi2.H>
+#include <p9_quad_power_off.H>
 
 /// @typedef p9_hcd_cache_initf_FP_t
 /// function pointer typedef definition for HWP call support
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
index ab5980f4..c374a23d 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
@@ -52,6 +52,26 @@
 // Function definitions
 // ----------------------------------------------------------------------
 
+#ifdef __PPE__
+uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+//    {0,    0},
+//    {5039, 0xE000000000000000}, //3
+//    {5100, 0xC1E061FFED5F0000}, //29
+//    {5664, 0xE000000000000000}, //3
+//    {5725, 0xC1E061FFED5F0000}, //29
+//    {5973, 0xE000000000000000}, //3
+//    {6034, 0xC1E061FFED5F0000}, //29
+//    {6282, 0xE000000000000000}, //3
+//    {6343, 0xC1E061FFED5F0000}, //29
+//    {17871, 0}                  //128
+const uint64_t G_ring_index[10] =
+{
+    0, 5039, 5100, 5664, 5725, 5973, 6034, 6282, 6343, 17871,
+};
+#endif
+
+
 // Procedure p9_quad_power_off entry point, comments in header
 fapi2::ReturnCode p9_quad_power_off(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
@@ -61,12 +81,95 @@ fapi2::ReturnCode p9_quad_power_off(
     constexpr uint32_t MAX_CORE_PER_QUAD = 4;
     fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS;
     uint32_t l_cnt = 0;
+#ifdef __PPE__
+    uint8_t  l_isMpipl = 0;
+    uint8_t  l_isRingSaveMpipl = 0;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
+             "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
+#endif
 
     FAPI_INF("p9_quad_power_off: Entering...");
 
     // Print chiplet position
     FAPI_INF("Quad power off chiplet no.%d", i_target.getChipletNumber());
 
+#ifdef __PPE__
+
+    if (l_isMpipl && l_isRingSaveMpipl)
+    {
+        l_data64.setBit<4>();  //SCAN_REGION_PERV - scan clock region perv
+        l_data64.setBit<5>();  //SCAN_REGION_UNIT1 - scan clock region eqpb - pb
+        l_data64.setBit<11>(); //SCAN_REGION_UNIT7 - scan clock region pbieq - pb
+        l_data64.setBit<59>(); //SCAN_TYPE_INEX - scan chain idex (c14 asic)
+
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN_REGION_TYPE,
+                                l_data64));
+
+        l_data64.flush<0>().set(0xa5a5a5a5a5a5a5a5);
+
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN64,
+                                l_data64));
+
+        for(uint32_t l_spin = 1; l_spin < 10; l_spin++)
+        {
+            uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
+                                  0xE000000000000000 : 0xC1E061FFED5F0000;
+            l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+
+            FAPI_TRY(fapi2::putScom(i_target,
+                                    EQ_SCAN_LONG_ROTATE,
+                                    l_data64));
+            l_data64.flush<0>();
+
+            do
+            {
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_CPLT_STAT0,
+                                        l_data64));
+            }
+            while (l_data64.getBit<8>() == 0);
+
+            l_data64.flush<0>();
+
+            if (l_spin == 9)
+            {
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_SCAN64,
+                                        l_data64));
+
+                if(l_data64 != 0xa5a5a5a5a5a5a5a5)
+                {
+                    FAPI_ASSERT(false,
+                                fapi2::P9_PM_QUAD_POWEROFF_INCORRECT_EQ_SCAN64_VAL()
+                                .set_EQ_SCAN64_VAL(l_data64),
+                                "Incorrect Value from EQ_SCAN64, Expected Value [0xa5a5a5a5a5a5a5a5]");
+                }
+            }
+            else
+            {
+                l_data64.flush<0>();
+                FAPI_TRY(fapi2::getScom(i_target,
+                                        EQ_SCAN64,
+                                        l_data64));
+                G_ring_save[l_spin - 1] = l_scandata & l_data64;
+            }
+        }
+
+        l_data64.flush<0>();
+        FAPI_TRY(fapi2::putScom(i_target,
+                                EQ_SCAN_REGION_TYPE,
+                                l_data64));
+    }
+
+#endif
+
     FAPI_DBG("Disabling bits 20/22/24/26 in EQ_QPPM_QPMMR_CLEAR, to gain access"
              " to PFET controller, otherwise Quad Power off scom will fail");
     l_data64.setBit<20>();
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
index 05a8a62c..9c684aaf 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -48,6 +48,11 @@
 // Constant definitions
 //------------------------------------------------------------------------------
 
+#ifdef __PPE__
+    extern uint64_t G_ring_save[8];
+    extern const uint64_t G_ring_index[10];
+#endif
+
 // function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_quad_power_off_FP_t) (
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index b25fddbf..72a34d0d 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2319,6 +2319,22 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL 
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
   <!-- ******************************************************************** -->
   <!-- End Memory Section                                                   -->
   <!-- ******************************************************************** -->
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 2ada705f..bd94b49b 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -424,6 +424,10 @@ attribute tank
           <name>ATTR_CHIP_EC_FEATURE_HW401184</name>
           <virtual/>
   </entry>
+  <entry>
+          <name>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</name>
+          <virtual/>
+  </entry>
 
   <entry>
         <name>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</name>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
index c6c78274..e5fce113 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_initf_errors.xml
@@ -25,6 +25,12 @@
 
 <hwpErrors>
   <!-- ********************************************************************* -->
-  
+  <hwpError>
+    <rc>RC_P9_HCD_CACHE_INITF_INCORRECT_EQ_SCAN64_VAL</rc>
+    <description>
+        Data mis-match on EQ_SCAN64 
+    </description>
+    <ffdc>EQ_SCAN64_VAL</ffdc>
+  </hwpError>  
   <!-- ********************************************************************* -->
 </hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_quad_power_off_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_quad_power_off_errors.xml
index 8cadcd2d..f56be40c 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_quad_power_off_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_quad_power_off_errors.xml
@@ -25,6 +25,12 @@
 <!-- Error definitions for p9_quad_power_off procedure -->
 <hwpErrors>
   <!-- ********************************************************************* -->
-  
+  <hwpError>
+    <rc>RC_P9_PM_QUAD_POWEROFF_INCORRECT_EQ_SCAN64_VAL</rc>
+    <description>
+        Data mis-match on EQ_SCAN64 
+    </description>
+    <ffdc>EQ_SCAN64_VAL</ffdc>
+  </hwpError>  
   <!-- ********************************************************************* -->
 </hwpErrors>