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author | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-16 04:42:19 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-16 07:08:30 -0400 |
commit | ece97c0ee59eba8efa66aafe782b4a07c0de566a (patch) | |
tree | 9917e9ce99962fe7df35cef5ae1cd8e7d4c3bebc /src/import/chips/p9/xip | |
parent | c731ca00c7494aa48c8eed36179561c36d19220c (diff) | |
download | talos-sbe-ece97c0ee59eba8efa66aafe782b4a07c0de566a.tar.gz talos-sbe-ece97c0ee59eba8efa66aafe782b4a07c0de566a.zip |
Update file headers
Change-Id: Icdd7460d8e3213f9bbd3d52e7825242bc59fc9e9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29825
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/xip')
-rw-r--r-- | src/import/chips/p9/xip/Makefile | 2 | ||||
-rw-r--r-- | src/import/chips/p9/xip/p9_xip_image.c | 2 | ||||
-rw-r--r-- | src/import/chips/p9/xip/p9_xip_image.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/xip/Makefile b/src/import/chips/p9/xip/Makefile index b97ffc15..a337e063 100644 --- a/src/import/chips/p9/xip/Makefile +++ b/src/import/chips/p9/xip/Makefile @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: import/chips/p9/xip/Makefile $ +# $Source: src/import/chips/p9/xip/Makefile $ # # OpenPOWER sbe Project # diff --git a/src/import/chips/p9/xip/p9_xip_image.c b/src/import/chips/p9/xip/p9_xip_image.c index 0f9ce1f7..18621811 100644 --- a/src/import/chips/p9/xip/p9_xip_image.c +++ b/src/import/chips/p9/xip/p9_xip_image.c @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: import/chips/p9/xip/p9_xip_image.c $ */ +/* $Source: src/import/chips/p9/xip/p9_xip_image.c $ */ /* */ /* OpenPOWER sbe Project */ /* */ diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 09bc1aa5..06240326 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: import/chips/p9/xip/p9_xip_image.h $ */ +/* $Source: src/import/chips/p9/xip/p9_xip_image.h $ */ /* */ /* OpenPOWER sbe Project */ /* */ |