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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2019-05-13 13:27:07 +0200 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-05-16 22:58:05 -0500 |
| commit | f0d3622fbac5bd82e598fd0e9381647f4d9303ac (patch) | |
| tree | 4cd889f0477a6f259443cbea8936b69db7393408 /src/import/chips/p9/procedures | |
| parent | c54904f7b338cc81b81c85d32e21d5a17b3fbf07 (diff) | |
| download | talos-sbe-f0d3622fbac5bd82e598fd0e9381647f4d9303ac.tar.gz talos-sbe-f0d3622fbac5bd82e598fd0e9381647f4d9303ac.zip | |
p9_sbe_chiplet_reset: Add missing OB3 clock muxes for Axone
Change-Id: Ied8f97e50aedad42d9a3b5f7d2156743b3f89dc1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77289
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77372
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 77ff5a12..314f1475 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -902,7 +902,10 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus( { if (axone_only) { - FAPI_DBG("Mux settings n/a for OB3 - Axone"); + FAPI_DBG("mux settings for OB3 - Axone"); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<23>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>(i_clk_mux_value.getBit<27>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>(i_clk_mux_value.getBit<30>()); } else { |
