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| author | Tsung Yeung <tyeung@us.ibm.com> | 2019-06-06 18:38:40 -0400 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-06-14 13:52:24 -0500 |
| commit | c9667ef21a6ff17b0248bb53482b905e6c74b237 (patch) | |
| tree | b6fb7ceee0321e5f779df7d286960dbd4d69875e /src/import/chips/p9/procedures/xml | |
| parent | 8384a9660449b237d492f5a953e3e12d9deaaf49 (diff) | |
| download | talos-sbe-c9667ef21a6ff17b0248bb53482b905e6c74b237.tar.gz talos-sbe-c9667ef21a6ff17b0248bb53482b905e6c74b237.zip | |
Add polling after STR entry to ensure port is in STR before asserting RESETn
Change-Id: Ic28ca541a578daccc0b9df6d8ffa99622c9eda38
CQ:SW465520
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78505
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78869
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 62549b31..5e05a1b1 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -509,4 +509,17 @@ <priority>HIGH</priority> </callout> </hwpError> + + <hwpError> + <rc>RC_MSS_STR_NOT_ENTERED</rc> + <description>Indicates a MCA has not entered STR within the allotted time</description> + <ffdc>PROC_TARGET</ffdc> + <ffdc>MCA_POS</ffdc> + <ffdc>MCA_FARB6Q</ffdc> + <ffdc>STR_STATE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> </hwpErrors> |
